From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57650) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9vPs-0003yO-LJ for qemu-devel@nongnu.org; Mon, 06 Jun 2016 10:22:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9vPo-0002DV-0j for qemu-devel@nongnu.org; Mon, 06 Jun 2016 10:22:08 -0400 Received: from mail-vk0-x22f.google.com ([2607:f8b0:400c:c05::22f]:35176) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9vPn-0002Cs-Tm for qemu-devel@nongnu.org; Mon, 06 Jun 2016 10:22:03 -0400 Received: by mail-vk0-x22f.google.com with SMTP id d127so201279730vkh.2 for ; Mon, 06 Jun 2016 07:22:02 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1464974151-1231644-1-git-send-email-afarallax@yandex.ru> References: <1464974151-1231644-1-git-send-email-afarallax@yandex.ru> From: Peter Maydell Date: Mon, 6 Jun 2016 15:21:43 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH] target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Sorokin Cc: QEMU Developers , qemu-arm On 3 June 2016 at 18:15, Sergey Sorokin wrote: > Address size is 40-bit for the AArch32 stage 2 translation, > and t0sz can be negative (from -8 to 7), > so we need to adjust it to use the existing TTBR selecting logic. > > Signed-off-by: Sergey Sorokin > --- > target-arm/helper.c | 38 ++++++++++++++++++++++---------------- > @@ -7348,15 +7354,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, > } > } > t1sz = extract32(tcr->raw_tcr, 16, 6); > - if (va_size == 64) { > + if (aarch64) { > t1sz = MIN(t1sz, 39); > t1sz = MAX(t1sz, 16); > } I wonder if we should move the extraction of t1sz into the preceding if() -- then we could do the '3 bit field vs 6 bit field' thing the way we do for t0sz. Still, that's a cleanup for a different patch. Applied to target-arm.next, thanks. -- PMM