From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SEgLx-00034t-PT for qemu-devel@nongnu.org; Mon, 02 Apr 2012 08:27:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SEgLs-0000p0-TM for qemu-devel@nongnu.org; Mon, 02 Apr 2012 08:27:21 -0400 Received: from mail-gy0-f173.google.com ([209.85.160.173]:50597) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SEgLs-0000nN-Pk for qemu-devel@nongnu.org; Mon, 02 Apr 2012 08:27:16 -0400 Received: by ghrr14 with SMTP id r14so1598305ghr.4 for ; Mon, 02 Apr 2012 05:27:14 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1333363816-1691-7-git-send-email-berrange@redhat.com> References: <1333363816-1691-1-git-send-email-berrange@redhat.com> <1333363816-1691-7-git-send-email-berrange@redhat.com> Date: Mon, 2 Apr 2012 13:27:14 +0100 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 6/9] Fix bit test to use & instead of && and enable -Wlogical-op warning List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Daniel P. Berrange" Cc: Maksim Kozlov , Mitsyanko Igor , qemu-devel@nongnu.org, Evgeny Voevodin , Dmitry Solodkiy On 2 April 2012 11:50, Daniel P. Berrange wrote: > diff --git a/hw/exynos4210_uart.c b/hw/exynos4210_uart.c > index 73a9c18..4b20105 100644 > --- a/hw/exynos4210_uart.c > +++ b/hw/exynos4210_uart.c > @@ -246,7 +246,7 @@ static uint32_t exynos4210_uart_Tx_FIFO_trigger_level= (Exynos4210UartState *s) > =C2=A0 =C2=A0 uint32_t level =3D 0; > =C2=A0 =C2=A0 uint32_t reg; > > - =C2=A0 =C2=A0reg =3D (s->reg[I_(UFCON)] && UFCON_Tx_FIFO_TRIGGER_LEVEL)= >> > + =C2=A0 =C2=A0reg =3D (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) = >> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHI= FT; > > =C2=A0 =C2=A0 switch (s->channel) { > @@ -277,7 +277,7 @@ static void exynos4210_uart_update_irq(Exynos4210Uart= State *s) > =C2=A0 =C2=A0 =C2=A0*/ > =C2=A0 =C2=A0 if (s->reg[I_(UFCON)] && UFCON_FIFO_ENABLE) { > > - =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t count =3D (s->reg[I_(UFSTAT)] && UF= STAT_Tx_FIFO_COUNT) >> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t count =3D (s->reg[I_(UFSTAT)] & UFS= TAT_Tx_FIFO_COUNT) >> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UFSTAT_Tx_FIFO_CO= UNT_SHIFT; > > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (count <=3D exynos4210_uart_Tx_FIFO_trigge= r_level(s)) { Nice catch. Note that the '&& UFCON_FIFO_ENABLE' you can see in the context to the second hunk is also wrong and needs fixing. I'll take the exynos changes via arm-devs.next, but not the configure change. Please can you submit a version of the patch that only fixes the bugs and doesn't also change the gcc warning flags? thanks -- PMM