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From: Peter Maydell <peter.maydell@linaro.org>
Date: Thu, 22 May 2014 08:22:35 +0100
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Subject: Re: [Qemu-devel] [PATCH v3 16/22] target-arm: A64: Generalize ERET
	to various ELs
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To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Rob Herring <rob.herring@linaro.org>, Peter Crosthwaite <peter.crosthwaite@xilinx.com>, Fabian Aggeler <aggelerf@ethz.ch>, QEMU Developers <qemu-devel@nongnu.org>, Alexander Graf <agraf@suse.de>, John Williams <john.williams@xilinx.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, Christoffer Dall <christoffer.dall@linaro.org>, Richard Henderson <rth@twiddle.net>

On 22 May 2014 01:48, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> On Wed, May 21, 2014 at 08:20:20PM +0100, Peter Maydell wrote:
>> it needs to also fix the bit in the "returning to an exception
>> level which is 32 bit" which says "new_el = 0" since that's
>> not guaranteed to be true any more. (Also I think the register
>> mapping for AArch32 EL2/EL1 needs handling correctly.)
>
> I've tried to stay away from touching too much of the AArch32
> code as I haven't had a setup to test 64/32 transitions
> beyond a64/el1 and a32/el0.

OK; if we put in a TODO comment that we assume EL1..EL3
are 64 bit currently, we'll have a marker to come back and fix
later.

thanks
-- PMM