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Tue, 18 May 2021 08:58:39 -0700 (PDT) MIME-Version: 1.0 References: <20210429234201.125565-1-shashi.mallela@linaro.org> <20210429234201.125565-6-shashi.mallela@linaro.org> In-Reply-To: <20210429234201.125565-6-shashi.mallela@linaro.org> From: Peter Maydell Date: Tue, 18 May 2021 16:58:22 +0100 Message-ID: Subject: Re: [PATCH v3 5/8] hw/intc: GICv3 ITS Feature enablement To: Shashi Mallela Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leif Lindholm , QEMU Developers , qemu-arm , Radoslaw Biernacki Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 30 Apr 2021 at 00:42, Shashi Mallela wrote: > > Added properties to enable ITS feature and define qemu system > address space memory in gicv3 common,setup distributor and > redistributor registers to indicate LPI support. > > Signed-off-by: Shashi Mallela > --- > hw/intc/arm_gicv3_common.c | 13 +++++++++++++ > hw/intc/arm_gicv3_dist.c | 21 +++++++++++++++++++-- > hw/intc/arm_gicv3_redist.c | 30 +++++++++++++++++++++++++----- > hw/intc/gicv3_internal.h | 17 +++++++++++++++++ > include/hw/intc/arm_gicv3_common.h | 1 + > 5 files changed, 75 insertions(+), 7 deletions(-) > > diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c > index 58ef65f589..a55e91071a 100644 > --- a/hw/intc/arm_gicv3_common.c > +++ b/hw/intc/arm_gicv3_common.c > @@ -381,6 +381,16 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) > (1 << 24) | > (i << 8) | > (last << 4); > + > + if (s->lpi_enable) { > + s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS; > + > + if (!s->dma) { > + error_setg(errp, > + "Redist-ITS: Guest 'sysmem' reference link not set"); > + return; > + } > + } Can you put the "if (s->lpi_enable && !s->dma)" error-exit further up in the function with all the other error-checks, please? That way we do all our error-handling before we start allocating memory and doing other things. > } > } > > @@ -494,9 +504,12 @@ static Property arm_gicv3_common_properties[] = { > DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), > DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), > DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), > + DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), > DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), > DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, > redist_region_count, qdev_prop_uint32, uint32_t), > + DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, > + MemoryRegion *), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c > index b65f56f903..43e0ea4367 100644 > --- a/hw/intc/arm_gicv3_dist.c > +++ b/hw/intc/arm_gicv3_dist.c > @@ -366,12 +366,15 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, > return MEMTX_OK; > case GICD_TYPER: > { > + bool lpi_supported = false; > /* For this implementation: > * No1N == 1 (1-of-N SPI interrupts not supported) > * A3V == 1 (non-zero values of Affinity level 3 supported) > * IDbits == 0xf (we support 16-bit interrupt identifiers) > * DVIS == 0 (Direct virtual LPI injection not supported) > - * LPIS == 0 (LPIs not supported) > + * LPIS == 1 (LPIs are supported if affinity routing is enabled) > + * num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated > + * by GICD_TYPER.IDbits) > * MBIS == 0 (message-based SPIs not supported) > * SecurityExtn == 1 if security extns supported > * CPUNumber == 0 since for us ARE is always 1 > @@ -385,8 +388,22 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, > */ > bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); > > + /* > + * With securityextn on, LPIs are supported when affinity routing > + * is enabled for non-secure state and if off LPIs are supported > + * when affinity routing is enabled. > + */ > + if (s->lpi_enable) { > + if (sec_extn) { > + lpi_supported = (s->gicd_ctlr & GICD_CTLR_ARE_NS); > + } else { > + lpi_supported = (s->gicd_ctlr & GICD_CTLR_ARE); > + } > + } For our implementation, affinity routing is always enabled, so you don't need to make a distinction between s->lpi_enable and lpi_supported. > + > *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | > - (0xf << 19) | itlinesnumber; > + (lpi_supported << GICD_TYPER_LPIS_OFFSET) | (GICD_TYPER_IDBITS << > + GICD_TYPER_IDBITS_OFFSET) | itlinesnumber; Don't break the line after << like this, please; it's much easier to read if you break after '|' instead, because then the (...) bracketed expression stays on one line rather than being split. > return MEMTX_OK; > } > case GICD_IIDR: > diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c > index 8645220d61..7604ccdc83 100644 > --- a/hw/intc/arm_gicv3_redist.c > +++ b/hw/intc/arm_gicv3_redist.c > @@ -244,14 +244,22 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, > static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, > uint64_t value, MemTxAttrs attrs) > { > + uint64_t data; > + > switch (offset) { > case GICR_CTLR: > /* For our implementation, GICR_TYPER.DPGS is 0 and so all > * the DPG bits are RAZ/WI. We don't do anything asynchronously, > - * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't > - * implement LPIs) so Enable_LPIs is RES0. So there are no writable > - * bits for us. > + * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we > + * implement LPIs) so Enable_LPIs is programmable. > */ > + if (cs->gicr_typer & GICR_TYPER_PLPIS) { > + if (value & GICR_CTLR_ENABLE_LPIS) { > + cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS; > + } else { > + cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS; > + } > + } > return MEMTX_OK; > case GICR_STATUSR: > /* RAZ/WI for our implementation */ > @@ -275,7 +283,12 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, > cs->gicr_waker = value; > return MEMTX_OK; > case GICR_PROPBASER: > - cs->gicr_propbaser = deposit64(cs->gicr_propbaser, 0, 32, value); > + data = value; > + if (FIELD_EX64(data, GICR_PROPBASER, IDBITS) > GICD_TYPER_IDBITS) { > + data &= ~R_GICR_PROPBASER_IDBITS_MASK; > + data |= GICD_TYPER_IDBITS; > + } > + cs->gicr_propbaser = deposit64(cs->gicr_propbaser, 0, 32, data); This is still wrong. On v2 I said: # This isn't what the spec says happens. It says that if the value the guest writes # in this field is larger than GICD_TYPER.IDbits, then the GICD_TYPER.IDBits value # applies. That doesn't mean the value reads back as GICD_TYPER.IDBits. # # How you want to handle this depends on what's going on, but it probably mostly # looks like "code that cares about GICR_PROPBASER.IDBits will do # MIN(field_value, GICD_TYPER_IDBITS) to find the effective value of the field". > return MEMTX_OK; > case GICR_PROPBASER + 4: > cs->gicr_propbaser = deposit64(cs->gicr_propbaser, 32, 32, value); > @@ -395,9 +408,16 @@ static MemTxResult gicr_readll(GICv3CPUState *cs, hwaddr offset, > static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset, > uint64_t value, MemTxAttrs attrs) > { > + uint64_t data; > + > switch (offset) { > case GICR_PROPBASER: > - cs->gicr_propbaser = value; > + data = value; > + if (FIELD_EX64(data, GICR_PROPBASER, IDBITS) > GICD_TYPER_IDBITS) { > + data &= ~R_GICR_PROPBASER_IDBITS_MASK; > + data |= GICD_TYPER_IDBITS; > + } > + cs->gicr_propbaser = data; Ditto. thanks -- PMM