Re: [Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75

[Peter Maydell <peter.maydell@linaro.org>]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  hw/arm/virt.c      |  1 +
>  target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index c69a734878..06a155724c 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -174,6 +174,7 @@ static const char *valid_cpus[] = {
>      ARM_CPU_TYPE_NAME("cortex-a57"),
>      ARM_CPU_TYPE_NAME("cortex-a72"),
>      ARM_CPU_TYPE_NAME("cortex-a73"),
> +    ARM_CPU_TYPE_NAME("cortex-a75"),
>      ARM_CPU_TYPE_NAME("host"),
>      ARM_CPU_TYPE_NAME("max"),
>  };
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index d34aa3af75..325e0ecf17 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj)
>      define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
>  }
>
> +static void aarch64_a75_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
>


> +    cpu->reset_sctlr = 0x00c50838; /* ??? can't find it in a75 trm */

There are a couple of things interacting here.
Firstly, I think that architecturally the reset values
(and how much is actually a defined value rather than
UNKNOWN) can differ between SCTLR_EL1/2/3, plus the 32-bit
vs 64-bit have different values for a few bits, but we try
to just shoehorn everything into a single reset_sctlr field
(see https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg01559.html
and surrounding messages in that thread for discussion).

Secondly, for the cortex-a75,
https://developer.arm.com/docs/100403/latest/part-b-register-descriptions/aarch64-system-registers/sctlr_el3-system-control-register-el3

does specify the reset value for SCTLR_EL3:
bit 25 is controlled by an external signal (aka a
QOM property for us), bits 12 2 and 0 are specified
to reset to 0, and every other bit resets to an
UNKNOWN value. I would suggest that we make the
RES0 bits 0, the RES1 bits 1, and use 0 for all the
other UNKNOWN bits.

SCTLR_EL1 is similar (if resetting into EL1)
https://developer.arm.com/docs/100403/latest/part-b-register-descriptions/aarch64-system-registers/sctlr_el1-system-control-register-el1
with the slight wrinkle that you need to also check
the architectural spec for some bits, eg bit 0 has
no reset value listed in the TRM but architecturally
is required to reset to 0 if resetting into EL1.

thanks
-- PMM