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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Desnogues , qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 28 Apr 2020 at 18:26, Philippe Mathieu-Daud=C3=A9 = wrote: > > MIDR_EL1 a 64-bit system register with the top 32-bit being RES0. > > This fixes when compiling with -Werror=3Dconversion: > > target/arm/cpu64.c: In function =E2=80=98aarch64_max_initfn=E2=80=99: > target/arm/cpu64.c:628:21: error: conversion from =E2=80=98uint64_t=E2= =80=99 {aka =E2=80=98long unsigned int=E2=80=99} to =E2=80=98uint32_t=E2=80= =99 {aka =E2=80=98unsigned int=E2=80=99} may change value [-Werror=3Dconver= sion] > 628 | cpu->midr =3D t; > | ^ > > Suggested-by: Laurent Desnogues > Suggested-by: Peter Maydell > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Applied to target-arm.next, with the commit message fixed up to match the patch contents: target/arm: Use uint64_t for midr field in CPU state struct MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0. Represent it in QEMU's ARMCPU struct with a uint64_t, not a uint32_t. This fixes an error when compiling with -Werror=3Dconversion because we were manipulating the register value using a local uint64_t variable: target/arm/cpu64.c: In function =E2=80=98aarch64_max_initfn=E2=80=99: target/arm/cpu64.c:628:21: error: conversion from =E2=80=98uint64_t= =E2=80=99 {aka =E2=80=98long unsigned int=E2=80=99} to =E2=80=98uint32_t =E2=80= =99 {aka =E2=80=98unsigned int=E2=80=99} may change value [-Werror=3Dconversion] 628 | cpu->midr =3D t; | ^ and future-proofs us against a possible future architecture change using some of the top 32 bits. thanks -- PMM