Re: ldrd implementation issue?

[Peter Maydell <peter.maydell@linaro.org>]

On Mon, 17 Feb 2025 at 13:03, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 11 Feb 2025 at 10:46, Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > (added qemu-devel to the cc list)
> >
> > On Mon, 10 Feb 2025 at 17:26, Stu Grossman <stu.grossman@gmail.com> wrote:
> > >
> > > I've been getting SIGBUS cores with a bunch of user apps running under
> > > linux 5.15 and qemu-system-aarch64.  These happen to be 32 bit (T32?)
> > > programs.
>
> > > The fix is to defer the register stores till after both words have been
> > > read from memory.
> > >
> > > Here is my fix:
>
> [snip patch]
>
> > Yes, this fix looks correct to me. Can you provide a
> > Signed-off-by: tag for it? We can't accept it as a patch
> > without that. (I can do the other administrative tidying
> > up of it into a commit, but the signed-off-by is what says
> > you have the legal right and are happy to submit it to QEMU
> > under our license (LGPLv2.1+ in this case)).
>
> Hi -- this is just a nudge about whether you can provide
> a signed-off-by line for this fix. I'd love to take it,
> but can't without a signed-off-by. (Otherwise I'll have to
> reimplement it from scratch, which I'll do at some point.)

I had a closer look at our LDRD code, and I noticed that we also
have another bug where we're not implementing the "must be 64-bit
atomic if the address is 8-aligned" requirement. So I wrote some
patches which fix that, and also will fix the page-crossing bug
(because they mean we now ask the memory system to load 64 bits
and then split it out into the two destination registers, rather
than doing two separate 32-bit loads, so we will take the fault
before updating either register).

If you're interested in testing those patches you can find them here:
https://patchew.org/QEMU/20250227142746.1698904-1-peter.maydell@linaro.org/

Thanks again for reporting this bug.

-- PMM