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From: Peter Maydell <peter.maydell@linaro.org>
Date: Sat, 5 Sep 2015 14:02:39 +0100
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Subject: Re: [Qemu-devel] [PATCH] ARM targets: added ARM_FEATURE for
 Thumb-exception bit in system control register
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To: Mike Haben <mike.haben@virgin.net>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On 5 September 2015 at 12:28, Mike Haben <mike.haben@virgin.net> wrote:
> Most ARM cores switch unconditionally to ARM mode when an exception occurs;
> some Cortex variants have a "Thumb-exception enable" bit in the system
> control register that allows an unconditional switch to Thumb mode instead
> when handling exceptions.  The presence of this bit seems unrelated to the
> version of instruction set, and some earlier cores use the same bit (30) in
> the control register for a completely different purpose, so seems sensible
> to handle it as yet another ARM feature.

I think that SCTLR.TE is an ARMv7 feature -- it is documented
in the v7 ARM ARM, and in the v6 ARM ARM the bit is UNP/SBZP.
And the CPUs you've set your new feature bit on in this patch
are exactly the v7 CPUs.

So I think that we should just change the existing guard
(which requires FEATURE_V4T) to require FEATURE_V7 instead).
You're right that we need to specifically squash env->thumb
to false in the no-feature-present case, though.

thanks
-- PMM