From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VSz90-0003Si-3I for qemu-devel@nongnu.org; Sun, 06 Oct 2013 20:57:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VSz8v-0005bp-7Q for qemu-devel@nongnu.org; Sun, 06 Oct 2013 20:57:54 -0400 Received: from mail-la0-f45.google.com ([209.85.215.45]:59055) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VSz8v-0005bj-0M for qemu-devel@nongnu.org; Sun, 06 Oct 2013 20:57:49 -0400 Received: by mail-la0-f45.google.com with SMTP id eh20so4919653lab.4 for ; Sun, 06 Oct 2013 17:57:47 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <52519D54.4070102@suse.de> References: <52519D54.4070102@suse.de> From: Peter Maydell Date: Mon, 7 Oct 2013 09:57:26 +0900 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] Update the id of Vexpress Cortex-A9 from r0p0 to r0p1? List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Andreas_F=C3=A4rber?= Cc: Mian Yousaf Kaukab , QEMU Developers On 7 October 2013 02:26, Andreas F=C3=A4rber wrote: > Am 06.10.2013 14:10, schrieb Peter Maydell: >> The major thing we need is a mechanism for allowing at least the >> board, and possibly also the user, to specify properties of the cpu >> like "which rev/patchlevel is it" > > I believe I posted patches for that long ago, to clean up the PXA mess a > little... probably need to be rebased by now. Ideally rev/patch ought to be properties on the cortex-a9 container object -- there's at least one programmer-visible change to an SCU register layout between r0 and r2. -- PMM