Re: [PATCH for-7.1 08/11] hw/net: Add NPCM8XX PCS Module

[Peter Maydell <peter.maydell@linaro.org>]

On Tue, 5 Apr 2022 at 23:38, Hao Wu <wuhaotsh@google.com> wrote:
>
> The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
> PHY. This implementation contains all the default registers and
> the soft reset feature that are required to load the Linux kernel
> driver. Further features have not been implemented yet.
>
> Signed-off-by: Hao Wu <wuhaotsh@google.com>
> Reviewed-by: Titus Rwantare <titusr@google.com>

> +static uint16_t npcm_pcs_read_sr_ctl(NPCMPCSState *s, hwaddr offset)
> +{
> +    hwaddr regno = offset / sizeof(uint16_t);
> +
> +    if (regno >= NPCM_PCS_NR_SR_CTLS) {
> +        qemu_log_mask(LOG_GUEST_ERROR,
> +                      "%s: SR_CTL read offset 0x%04" HWADDR_PRIx
> +                      " is out of range.",

qemu_log_mask strings need to have a trailing "\n" (here and below)


> +static uint64_t npcm_pcs_read(void *opaque, hwaddr offset, unsigned size)
> +{
> +    NPCMPCSState *s = opaque;
> +    uint16_t v = 0;
> +
> +    if (offset == NPCM_PCS_IND_AC_BA) {
> +        v = s->indirect_access_base;
> +    } else {
> +        switch (s->indirect_access_base) {
> +        case NPCM_PCS_IND_SR_CTL:
> +            v = npcm_pcs_read_sr_ctl(s, offset);
> +            break;
> +
> +        case NPCM_PCS_IND_SR_MII:
> +            v = npcm_pcs_read_sr_mii(s, offset);
> +            break;
> +
> +        case NPCM_PCS_IND_SR_TIM:
> +            v = npcm_pcs_read_sr_tim(s, offset);
> +            break;
> +
> +        case NPCM_PCS_IND_VR_MII:
> +            v = npcm_pcs_read_vr_mii(s, offset);
> +            break;
> +
> +        default:
> +            qemu_log_mask(LOG_GUEST_ERROR,
> +                          "%s: Read with invalid indirect address base: 0x%02"

Why are you specifying a width of 2 here? The valid values are definitely
larger than 2 digits wide, so presumably invalid values probably are as well...

> +                          PRIx16 "\n", DEVICE(s)->canonical_path,
> +                          s->indirect_access_base);
> +        }
> +    }
> +
> +    trace_npcm_pcs_reg_read(DEVICE(s)->canonical_path, s->indirect_access_base,
> +                            offset, v);
> +    return v;
> +}

> +static void npcm_pcs_class_init(ObjectClass *klass, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +
> +    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);

Not sure this is the right category -- this doesn't seem to
be a network device in the usual sense.


> +# npcm_pcs.c
> +npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
> +npcm_pcs_reg_write(const char *name, uint16_t indirect_access_baes, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16

Typo : should be "_base" I assume.


> +
>  # dp8398x.c
>  dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x"
>  dp8393x_lower_irq(void) "lower irq"
> diff --git a/include/hw/net/npcm_pcs.h b/include/hw/net/npcm_pcs.h
> new file mode 100644
> index 0000000000..bd4f71bf3c
> --- /dev/null
> +++ b/include/hw/net/npcm_pcs.h
> @@ -0,0 +1,42 @@
> +/*
> + * Nuvoton NPCM8xx PCS Module
> + *
> + * Copyright 2022 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + */
> +
> +#ifndef NPCM_PCS_H
> +#define NPCM_PCS_H
> +
> +#include "hw/sysbus.h"
> +
> +#define NPCM_PCS_NR_SR_CTLS     (0x12 / sizeof(uint16_t))
> +#define NPCM_PCS_NR_SR_MIIS     (0x20 / sizeof(uint16_t))
> +#define NPCM_PCS_NR_SR_TIMS     (0x22 / sizeof(uint16_t))
> +#define NPCM_PCS_NR_VR_MIIS     (0x1c6 / sizeof(uint16_t))
> +
> +typedef struct NPCMPCSState {
> +    SysBusDevice parent;
> +
> +    MemoryRegion iomem;
> +
> +    uint16_t indirect_access_base;
> +    uint16_t sr_ctl[NPCM_PCS_NR_SR_CTLS];
> +    uint16_t sr_mii[NPCM_PCS_NR_SR_MIIS];
> +    uint16_t sr_tim[NPCM_PCS_NR_SR_TIMS];
> +    uint16_t vr_mii[NPCM_PCS_NR_VR_MIIS];
> +} NPCMPCSState;
> +
> +#define TYPE_NPCM_PCS "npcm-pcs"
> +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCSState, NPCM_PCS)

OBJECT_DECLARE_SIMPLE_TYPE does the 'typedef' for you, so you
don't need to do that in your struct definition if you're using that
macro.

thanks
-- PMM