From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGBQD-0006Ei-UK for qemu-devel@nongnu.org; Tue, 27 Jan 2015 14:03:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YGBQ8-0005sY-VL for qemu-devel@nongnu.org; Tue, 27 Jan 2015 14:03:33 -0500 Received: from mail-lb0-f174.google.com ([209.85.217.174]:33243) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGBQ8-0005sU-P7 for qemu-devel@nongnu.org; Tue, 27 Jan 2015 14:03:28 -0500 Received: by mail-lb0-f174.google.com with SMTP id f15so14807253lbj.5 for ; Tue, 27 Jan 2015 11:03:28 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1422029835-4696-5-git-send-email-greg.bellows@linaro.org> References: <1422029835-4696-1-git-send-email-greg.bellows@linaro.org> <1422029835-4696-5-git-send-email-greg.bellows@linaro.org> From: Peter Maydell Date: Tue, 27 Jan 2015 19:03:07 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: QEMU Developers On 23 January 2015 at 16:17, Greg Bellows wrote: > Added CP register definitions for SP_EL1 and SP_EL2. > > Signed-off-by: Greg Bellows > Reviewed-by: Peter Maydell > > --- > > v1 -> v2 > - Remove unnecessary accessfn for SP_EL1/2 > - Revert SP_EL0 accessfn name to sp_el0_access > --- > target-arm/helper.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 29f3b62..79c54a9 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > .access = PL1_RW, .accessfn = sp_el0_access, > .type = ARM_CP_NO_MIGRATE, > .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, > + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, > + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE, > + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, > { .name = "SPSel", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, > .type = ARM_CP_NO_MIGRATE, > @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > .access = PL2_RW, .writefn = vbar_write, > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), > .resetvalue = 0 }, > + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, > + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE, > + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, > REGINFO_SENTINEL > }; As I was assembling my target-arm queue I found that this patch and the 'split ARM_CP_NO_MIGRATE' patch semantically conflict; since this patch happened to be earlier in the queue than that one, I've resolved this by adding changes to the 'split' patch which change these ARM_CP_NO_MIGRATE uses to ARM_CP_ALIAS, in line with how we handled the SP_EL0 regdef. thanks -- PMM