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Tue, 12 Jan 2021 02:49:08 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> In-Reply-To: <20210110081429.10126-3-bmeng.cn@gmail.com> From: Peter Maydell Date: Tue, 12 Jan 2021 10:48:57 +0000 Message-ID: Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , Alistair Francis , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: > > From: Bin Meng > > Usually the approach is that the device on the other end of the line > is going to reset its state anyway, so there's no need to actively > signal an irq line change during the reset hook. > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > imx_spi_hard_reset() that is called when the controller is disabled. > > Signed-off-by: Bin Meng > > --- > > Changes in v4: > - adujst the patch 2,3 order > - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion > > Changes in v3: > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > hw/ssi/imx_spi.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index e605049a21..2c4c5ec1b8 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) > imx_spi_rxfifo_reset(s); > imx_spi_txfifo_reset(s); > > - imx_spi_update_irq(s); > - > s->burst_length = 0; > } > > +static void imx_spi_hard_reset(IMXSPIState *s) > +{ > + imx_spi_reset(DEVICE(s)); > + > + imx_spi_update_irq(s); > +} > + > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) > { > uint32_t value = 0; > @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > s->regs[ECSPI_CONREG] = value; > > if (!imx_spi_is_enabled(s)) { > - /* device is disabled, so this is a reset */ > - imx_spi_reset(DEVICE(s)); > + /* device is disabled, so this is a hard reset */ > + imx_spi_hard_reset(s); > + > return; > } The function of the code is correct, but you seem to have the function naming backwards here. Generally: * soft reset == the reset triggered by the register write * hard reset == power-on reset == the dc->reset function I think this is what Philippe was trying to say. thanks -- PMM