Re: [Qemu-devel] [PATCH v2 04/15] target/arm: Handle SVE vector length changes in system mode

Re: [Qemu-devel] [PATCH v2 04/15] target/arm: Handle SVE vector length changes in system mode

[Peter Maydell]

On 26 September 2018 at 20:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
> SVE vector length can change when changing EL, or when writing
> to one of the ZCR_ELn registers.
>
> For correctness, our implementation requires that predicate bits
> that are inaccessible are never set.  Which means noticing length
> changes and zeroing the appropriate register bits.
>
> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> +
> +/*
> + * Notice a change in SVE vector size when changing EL.
> + */
> +void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el)
> +{
> +    int old_len, new_len;
> +
> +    /* Nothing to do if no SVE.  */
> +    if (!arm_feature(env, ARM_FEATURE_SVE)) {
> +        return;
> +    }
> +
> +    /* Nothing to do if FP is disabled in either EL.  */
> +    if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
> +        return;
> +    }
> +
> +    /*
> +     * When FP is enabled, but SVE is disabled, the effective len is 0.
> +     * ??? Do we need a conditional for old_el/new_el in aa32 state?
> +     * That isn't included in the CheckSVEEnabled pseudocode, so is the
> +     * host kernel required to explicitly disable SVE for an EL using aa32?
> +     */

Possibly relevant here is DDI0584A.d section 3.2 (that's the
SVE Arm ARM supplement), which says "If SVE instructions are
disabled or trapped at ELx, or not available because that Exception
level is in AArch32 state, then for all purposes other than a direct
read, the ZCR_ELx.LEN field has an Effective value of 0".

My assumption is that the CheckSVEEnabled pseudacode doesn't look
for the exception level being AArch32 because it's not possible
to reach that function in AArch32 mode.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v2 03/15] target/arm: Pass in current_el to fp and sve_exception_el

[Peter Maydell]

On 26 September 2018 at 20:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
> We are going to want to determine whether sve is enabled
> for EL other than current.
>
> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH v2 05/15] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE

[Peter Maydell]

On 26 September 2018 at 20:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Use the existing helpers to determine if (1) the fpu is enabled,
> (2) sve state is enabled, and (3) the current sve vector length.
>
> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH v2 06/15] target/arm: Clear unused predicate bits for LD1RQ

[Peter Maydell]

On 26 September 2018 at 20:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
> The 16-byte load only uses 16 predicate bits.  But while
> reusing the other load infrastructure, we find other bits
> that are set and trigger an assert.  To avoid this and
> retain the assert, zero-extend the predicate that we pass
> to the LD1 helper.
>
> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH v2 07/15] target/arm: Rewrite helper_sve_ld1*_r using pages

[Peter Maydell]

On 26 September 2018 at 20:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Uses tlb_vaddr_to_host for correct operation with softmmu.
> Optimize for accesses within a single page or pair of pages.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---


Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM