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* [PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
@ 2023-09-22 18:14 Chris Rauer
  2023-09-22 18:24 ` Hao Wu
  2023-10-17 13:18 ` Peter Maydell
  0 siblings, 2 replies; 4+ messages in thread
From: Chris Rauer @ 2023-09-22 18:14 UTC (permalink / raw)
  To: peter.maydell, kfting, wuhaotsh; +Cc: qemu-arm, qemu-devel, Chris Rauer

The counter register is only 24-bits and counts down.  If the timer is
running but the qtimer to reset it hasn't fired off yet, there is a chance
the regster read can return an invalid result.

Signed-off-by: Chris Rauer <crauer@google.com>
---
 hw/timer/npcm7xx_timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index 32f5e021f8..a8bd93aeb2 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -138,6 +138,9 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
 /* Convert a time interval in nanoseconds to a timer cycle count. */
 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 {
+    if (ns < 0) {
+        return 0;
+    }
     return clock_ns_to_ticks(t->ctrl->clock, ns) /
         npcm7xx_tcsr_prescaler(t->tcsr);
 }
-- 
2.42.0.515.g380fc7ccd1-goog



^ permalink raw reply related	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-10-17 13:19 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2023-09-22 18:14 [PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero Chris Rauer
2023-09-22 18:24 ` Hao Wu
2023-09-22 21:20   ` Chris Rauer
2023-10-17 13:18 ` Peter Maydell

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