* [PULL 01/18] arm/kvm: add support for MTE
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 02/18] docs/system/cpu-hotplug: Update example's socket-id/core-id Peter Maydell
` (17 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
From: Cornelia Huck <cohuck@redhat.com>
Extend the 'mte' property for the virt machine to cover KVM as
well. For KVM, we don't allocate tag memory, but instead enable
the capability.
If MTE has been enabled, we need to disable migration, as we do not
yet have a way to migrate the tags as well. Therefore, MTE will stay
off with KVM unless requested explicitly.
[gankulkarni: This patch is rework of commit b320e21c48
which broke TCG since it made the TCG -cpu max
report the presence of MTE to the guest even if the board hadn't
enabled MTE by wiring up the tag RAM. This meant that if the guest
then tried to use MTE QEMU would segfault accessing the
non-existent tag RAM.]
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
Message-id: 20241008114302.4855-1-gankulkarni@os.amperecomputing.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 2 ++
target/arm/kvm_arm.h | 19 +++++++++++
hw/arm/virt.c | 76 +++++++++++++++++++++++++-------------------
target/arm/cpu.c | 14 ++++++--
target/arm/kvm.c | 58 +++++++++++++++++++++++++++++++++
5 files changed, 134 insertions(+), 35 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f065756c5c7..8fc8b6398f7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -922,6 +922,8 @@ struct ArchCPU {
/* CPU has memory protection unit */
bool has_mpu;
+ /* CPU has MTE enabled in KVM mode */
+ bool kvm_mte;
/* PMSAv7 MPU number of supported regions */
uint32_t pmsav7_dregion;
/* PMSAv8 MPU number of supported hyp regions */
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index cfaa0d9bc71..4d293618a78 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -188,6 +188,13 @@ bool kvm_arm_pmu_supported(void);
*/
bool kvm_arm_sve_supported(void);
+/**
+ * kvm_arm_mte_supported:
+ *
+ * Returns: true if KVM can enable MTE, and false otherwise.
+ */
+bool kvm_arm_mte_supported(void);
+
/**
* kvm_arm_get_max_vm_ipa_size:
* @ms: Machine state handle
@@ -214,6 +221,8 @@ void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa);
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
+void kvm_arm_enable_mte(Object *cpuobj, Error **errp);
+
#else
/*
@@ -235,6 +244,11 @@ static inline bool kvm_arm_sve_supported(void)
return false;
}
+static inline bool kvm_arm_mte_supported(void)
+{
+ return false;
+}
+
/*
* These functions should never actually be called without KVM support.
*/
@@ -283,6 +297,11 @@ static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)
g_assert_not_reached();
}
+static inline void kvm_arm_enable_mte(Object *cpuobj, Error **errp)
+{
+ g_assert_not_reached();
+}
+
#endif
#endif
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 8b2b991d978..1a381e9a2bd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2213,7 +2213,7 @@ static void machvirt_init(MachineState *machine)
exit(1);
}
- if (vms->mte && (kvm_enabled() || hvf_enabled())) {
+ if (vms->mte && hvf_enabled()) {
error_report("mach-virt: %s does not support providing "
"MTE to the guest CPU",
current_accel_name());
@@ -2283,39 +2283,51 @@ static void machvirt_init(MachineState *machine)
}
if (vms->mte) {
- /* Create the memory region only once, but link to all cpus. */
- if (!tag_sysmem) {
- /*
- * The property exists only if MemTag is supported.
- * If it is, we must allocate the ram to back that up.
- */
- if (!object_property_find(cpuobj, "tag-memory")) {
- error_report("MTE requested, but not supported "
- "by the guest CPU");
+ if (tcg_enabled()) {
+ /* Create the memory region only once, but link to all cpus. */
+ if (!tag_sysmem) {
+ /*
+ * The property exists only if MemTag is supported.
+ * If it is, we must allocate the ram to back that up.
+ */
+ if (!object_property_find(cpuobj, "tag-memory")) {
+ error_report("MTE requested, but not supported "
+ "by the guest CPU");
+ exit(1);
+ }
+
+ tag_sysmem = g_new(MemoryRegion, 1);
+ memory_region_init(tag_sysmem, OBJECT(machine),
+ "tag-memory", UINT64_MAX / 32);
+
+ if (vms->secure) {
+ secure_tag_sysmem = g_new(MemoryRegion, 1);
+ memory_region_init(secure_tag_sysmem, OBJECT(machine),
+ "secure-tag-memory",
+ UINT64_MAX / 32);
+
+ /* As with ram, secure-tag takes precedence over tag. */
+ memory_region_add_subregion_overlap(secure_tag_sysmem,
+ 0, tag_sysmem, -1);
+ }
+ }
+
+ object_property_set_link(cpuobj, "tag-memory",
+ OBJECT(tag_sysmem), &error_abort);
+ if (vms->secure) {
+ object_property_set_link(cpuobj, "secure-tag-memory",
+ OBJECT(secure_tag_sysmem),
+ &error_abort);
+ }
+ } else if (kvm_enabled()) {
+ if (!kvm_arm_mte_supported()) {
+ error_report("MTE requested, but not supported by KVM");
exit(1);
}
-
- tag_sysmem = g_new(MemoryRegion, 1);
- memory_region_init(tag_sysmem, OBJECT(machine),
- "tag-memory", UINT64_MAX / 32);
-
- if (vms->secure) {
- secure_tag_sysmem = g_new(MemoryRegion, 1);
- memory_region_init(secure_tag_sysmem, OBJECT(machine),
- "secure-tag-memory", UINT64_MAX / 32);
-
- /* As with ram, secure-tag takes precedence over tag. */
- memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
- tag_sysmem, -1);
- }
- }
-
- object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
- &error_abort);
- if (vms->secure) {
- object_property_set_link(cpuobj, "secure-tag-memory",
- OBJECT(secure_tag_sysmem),
- &error_abort);
+ kvm_arm_enable_mte(cpuobj, &error_abort);
+ } else {
+ error_report("MTE requested, but not supported ");
+ exit(1);
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1320fd8c8fe..5b751439bdc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2390,14 +2390,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
/*
- * If we do not have tag-memory provided by the machine,
- * reduce MTE support to instructions enabled at EL0.
+ * If we run with TCG and do not have tag-memory provided by
+ * the machine, then reduce MTE support to instructions enabled at EL0.
* This matches Cortex-A710 BROADCASTMTE input being LOW.
*/
- if (cpu->tag_memory == NULL) {
+ if (tcg_enabled() && cpu->tag_memory == NULL) {
cpu->isar.id_aa64pfr1 =
FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
}
+
+ /*
+ * If MTE is supported by the host, however it should not be
+ * enabled on the guest (i.e mte=off), clear guest's MTE bits."
+ */
+ if (kvm_enabled() && !cpu->kvm_mte) {
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+ }
#endif
}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index f1f1b5b375a..000afa03631 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -39,6 +39,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/ghes.h"
#include "target/arm/gtimer.h"
+#include "migration/blocker.h"
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
@@ -119,6 +120,21 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
if (vmfd < 0) {
goto err;
}
+
+ /*
+ * The MTE capability must be enabled by the VMM before creating
+ * any VCPUs in order to allow the MTE bits of the ID_AA64PFR1
+ * register to be probed correctly, as they are masked if MTE
+ * is not enabled.
+ */
+ if (kvm_arm_mte_supported()) {
+ KVMState kvm_state;
+
+ kvm_state.fd = kvmfd;
+ kvm_state.vmfd = vmfd;
+ kvm_vm_enable_cap(&kvm_state, KVM_CAP_ARM_MTE, 0);
+ }
+
cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0);
if (cpufd < 0) {
goto err;
@@ -1793,6 +1809,11 @@ bool kvm_arm_sve_supported(void)
return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
}
+bool kvm_arm_mte_supported(void)
+{
+ return kvm_check_extension(kvm_state, KVM_CAP_ARM_MTE);
+}
+
QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)
@@ -2417,3 +2438,40 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
}
return 0;
}
+
+void kvm_arm_enable_mte(Object *cpuobj, Error **errp)
+{
+ static bool tried_to_enable;
+ static bool succeeded_to_enable;
+ Error *mte_migration_blocker = NULL;
+ ARMCPU *cpu = ARM_CPU(cpuobj);
+ int ret;
+
+ if (!tried_to_enable) {
+ /*
+ * MTE on KVM is enabled on a per-VM basis (and retrying doesn't make
+ * sense), and we only want a single migration blocker as well.
+ */
+ tried_to_enable = true;
+
+ ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_ARM_MTE, 0);
+ if (ret) {
+ error_setg_errno(errp, -ret, "Failed to enable KVM_CAP_ARM_MTE");
+ return;
+ }
+
+ /* TODO: Add migration support with MTE enabled */
+ error_setg(&mte_migration_blocker,
+ "Live migration disabled due to MTE enabled");
+ if (migrate_add_blocker(&mte_migration_blocker, errp)) {
+ error_free(mte_migration_blocker);
+ return;
+ }
+
+ succeeded_to_enable = true;
+ }
+
+ if (succeeded_to_enable) {
+ cpu->kvm_mte = true;
+ }
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 02/18] docs/system/cpu-hotplug: Update example's socket-id/core-id
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
2024-10-29 15:10 ` [PULL 01/18] arm/kvm: add support for MTE Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr Peter Maydell
` (16 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
The example of how to do vCPU hotplug and hot-unlpug in the
cpu-hotplug documentation no longer works, because the way we
allocate socket-id and core-id to CPUs by default has changed at some
point. The output also no longer matches what current QEMU produces
in some more cosmetic ways.
Update the example to match current QEMU. The differences are:
* the second CPU is now socket-id=0 core-id=1,
not socket-id=1 core-id=0
* the order of fields in QMP responses is now in alphabetical order
* the "arch" member is no longer present in the query-cpus-fast
output (it was removed in QEMU 6.0)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20241010131800.3210161-1-peter.maydell@linaro.org
Message-id: 20240819144303.37852-1-peter.maydell@linaro.org
---
docs/system/cpu-hotplug.rst | 56 ++++++++++++++++++-------------------
1 file changed, 27 insertions(+), 29 deletions(-)
diff --git a/docs/system/cpu-hotplug.rst b/docs/system/cpu-hotplug.rst
index 015ce2b6ec3..cc50937c36c 100644
--- a/docs/system/cpu-hotplug.rst
+++ b/docs/system/cpu-hotplug.rst
@@ -33,23 +33,23 @@ vCPU hotplug
{
"return": [
{
- "type": "IvyBridge-IBRS-x86_64-cpu",
- "vcpus-count": 1,
"props": {
- "socket-id": 1,
- "core-id": 0,
+ "core-id": 1,
+ "socket-id": 0,
"thread-id": 0
- }
+ },
+ "type": "IvyBridge-IBRS-x86_64-cpu",
+ "vcpus-count": 1
},
{
+ "props": {
+ "core-id": 0,
+ "socket-id": 0,
+ "thread-id": 0
+ },
"qom-path": "/machine/unattached/device[0]",
"type": "IvyBridge-IBRS-x86_64-cpu",
- "vcpus-count": 1,
- "props": {
- "socket-id": 0,
- "core-id": 0,
- "thread-id": 0
- }
+ "vcpus-count": 1
}
]
}
@@ -58,18 +58,18 @@ vCPU hotplug
(4) The ``query-hotpluggable-cpus`` command returns an object for CPUs
that are present (containing a "qom-path" member) or which may be
hot-plugged (no "qom-path" member). From its output in step (3), we
- can see that ``IvyBridge-IBRS-x86_64-cpu`` is present in socket 0,
- while hot-plugging a CPU into socket 1 requires passing the listed
+ can see that ``IvyBridge-IBRS-x86_64-cpu`` is present in socket 0 core 0,
+ while hot-plugging a CPU into socket 0 core 1 requires passing the listed
properties to QMP ``device_add``::
- (QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=1 core-id=0 thread-id=0
+ (QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=0 core-id=1 thread-id=0
{
"execute": "device_add",
"arguments": {
- "socket-id": 1,
+ "core-id": 1,
"driver": "IvyBridge-IBRS-x86_64-cpu",
"id": "cpu-2",
- "core-id": 0,
+ "socket-id": 0,
"thread-id": 0
}
}
@@ -83,34 +83,32 @@ vCPU hotplug
(QEMU) query-cpus-fast
{
- "execute": "query-cpus-fast",
"arguments": {}
+ "execute": "query-cpus-fast",
}
{
"return": [
{
- "qom-path": "/machine/unattached/device[0]",
- "target": "x86_64",
- "thread-id": 11534,
"cpu-index": 0,
"props": {
- "socket-id": 0,
"core-id": 0,
+ "socket-id": 0,
"thread-id": 0
},
- "arch": "x86"
+ "qom-path": "/machine/unattached/device[0]",
+ "target": "x86_64",
+ "thread-id": 28957
},
{
- "qom-path": "/machine/peripheral/cpu-2",
- "target": "x86_64",
- "thread-id": 12106,
"cpu-index": 1,
"props": {
- "socket-id": 1,
- "core-id": 0,
+ "core-id": 1,
+ "socket-id": 0,
"thread-id": 0
},
- "arch": "x86"
+ "qom-path": "/machine/peripheral/cpu-2",
+ "target": "x86_64",
+ "thread-id": 29095
}
]
}
@@ -123,10 +121,10 @@ From the 'qmp-shell', invoke the QMP ``device_del`` command::
(QEMU) device_del id=cpu-2
{
- "execute": "device_del",
"arguments": {
"id": "cpu-2"
}
+ "execute": "device_del",
}
{
"return": {}
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
2024-10-29 15:10 ` [PULL 01/18] arm/kvm: add support for MTE Peter Maydell
2024-10-29 15:10 ` [PULL 02/18] docs/system/cpu-hotplug: Update example's socket-id/core-id Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-31 16:55 ` Michael Tokarev
2024-10-29 15:10 ` [PULL 04/18] target/arm: Don't assert in regime_is_user() for E10 mmuidx values Peter Maydell
` (15 subsequent siblings)
18 siblings, 1 reply; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Currently we store the FPSR cumulative exception bits in the
float_status fields, and use env->vfp.fpsr only for the NZCV bits.
(The QC bit is stored in env->vfp.qc[].)
This works for TCG, but if QEMU was built without CONFIG_TCG (i.e.
with KVM support only) then we use the stub versions of
vfp_get_fpsr_from_host() and vfp_set_fpsr_to_host() which do nothing,
throwing away the cumulative exception bit state. The effect is that
if the FPSR state is round-tripped from KVM to QEMU then we lose the
cumulative exception bits. In particular, this will happen if the VM
is migrated. There is no user-visible bug when using KVM with a QEMU
binary that was built with CONFIG_TCG.
Fix this by always storing the cumulative exception bits in
env->vfp.fpsr. If we are using TCG then we may also keep pending
cumulative exception information in the float_status fields, so we
continue to fold that in on reads.
This change will also be helpful for implementing FEAT_AFP later,
because that includes a feature where in some situations we want to
cause input denormals to be flushed to zero without affecting the
existing state of the FPSR.IDC bit, so we need a place to store IDC
which is distinct from the various float_status fields.
(Note for stable backports: the bug goes back to 4a15527c9fee but
this code was refactored in commits ea8618382aba..a8ab8706d4cc461, so
fixing it in branches without those refactorings will mean either
backporting the refactor or else implementing a conceptually similar
fix for the old code.)
Cc: qemu-stable@nongnu.org
Fixes: 4a15527c9fee ("target/arm/vfp_helper: Restrict the SoftFloat use to TCG")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241011162401.3672735-1-peter.maydell@linaro.org
---
target/arm/vfp_helper.c | 56 ++++++++++++-----------------------------
1 file changed, 16 insertions(+), 40 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 203d37303bd..62638d2b1f9 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -59,32 +59,6 @@ static inline int vfp_exceptbits_from_host(int host_bits)
return target_bits;
}
-/* Convert vfp exception flags to target form. */
-static inline int vfp_exceptbits_to_host(int target_bits)
-{
- int host_bits = 0;
-
- if (target_bits & 1) {
- host_bits |= float_flag_invalid;
- }
- if (target_bits & 2) {
- host_bits |= float_flag_divbyzero;
- }
- if (target_bits & 4) {
- host_bits |= float_flag_overflow;
- }
- if (target_bits & 8) {
- host_bits |= float_flag_underflow;
- }
- if (target_bits & 0x10) {
- host_bits |= float_flag_inexact;
- }
- if (target_bits & 0x80) {
- host_bits |= float_flag_input_denormal;
- }
- return host_bits;
-}
-
static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
{
uint32_t i;
@@ -99,15 +73,14 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
return vfp_exceptbits_from_host(i);
}
-static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
+static void vfp_clear_float_status_exc_flags(CPUARMState *env)
{
/*
- * The exception flags are ORed together when we read fpscr so we
- * only need to preserve the current state in one of our
- * float_status values.
+ * Clear out all the exception-flag information in the float_status
+ * values. The caller should have arranged for env->vfp.fpsr to
+ * be the architecturally up-to-date exception flag information first.
*/
- int i = vfp_exceptbits_to_host(val);
- set_float_exception_flags(i, &env->vfp.fp_status);
+ set_float_exception_flags(0, &env->vfp.fp_status);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
set_float_exception_flags(0, &env->vfp.standard_fp_status);
set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
@@ -164,7 +137,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
return 0;
}
-static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
+static void vfp_clear_float_status_exc_flags(CPUARMState *env)
{
}
@@ -216,8 +189,6 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
{
ARMCPU *cpu = env_archcpu(env);
- vfp_set_fpsr_to_host(env, val);
-
if (arm_feature(env, ARM_FEATURE_NEON) ||
cpu_isar_feature(aa32_mve, cpu)) {
/*
@@ -231,13 +202,18 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
}
/*
- * The only FPSR bits we keep in vfp.fpsr are NZCV:
- * the exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
- * fp_status, and QC is in vfp.qc[]. Store the NZCV bits there,
- * and zero any of the other FPSR bits.
+ * NZCV lives only in env->vfp.fpsr. The cumulative exception flags
+ * IOC|DZC|OFC|UFC|IXC|IDC also live in env->vfp.fpsr, with possible
+ * extra pending exception information that hasn't yet been folded in
+ * living in the float_status values (for TCG).
+ * Since this FPSR write gives us the up to date values of the exception
+ * flags, we want to store into vfp.fpsr the NZCV and CEXC bits, zeroing
+ * anything else. We also need to clear out the float_status exception
+ * information so that the next vfp_get_fpsr does not fold in stale data.
*/
- val &= FPSR_NZCV_MASK;
+ val &= FPSR_NZCV_MASK | FPSR_CEXC_MASK;
env->vfp.fpsr = val;
+ vfp_clear_float_status_exc_flags(env);
}
static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask)
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
2024-10-29 15:10 ` [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr Peter Maydell
@ 2024-10-31 16:55 ` Michael Tokarev
2024-10-31 17:01 ` Peter Maydell
0 siblings, 1 reply; 25+ messages in thread
From: Michael Tokarev @ 2024-10-31 16:55 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel, qemu-stable
29.10.2024 18:10, Peter Maydell wrote:
...
> (Note for stable backports: the bug goes back to 4a15527c9fee but
> this code was refactored in commits ea8618382aba..a8ab8706d4cc461, so
> fixing it in branches without those refactorings will mean either
> backporting the refactor or else implementing a conceptually similar
> fix for the old code.)
What do you think is the better way here -- pick up the refactoring
changes (to 9.0 and earlier), do a backport of this single fix, or
do nothing? Note for 7.2 branch it probably requires quite a bit
more work.
Thanks,
/mjt
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
2024-10-31 16:55 ` Michael Tokarev
@ 2024-10-31 17:01 ` Peter Maydell
2024-10-31 17:31 ` Michael Tokarev
0 siblings, 1 reply; 25+ messages in thread
From: Peter Maydell @ 2024-10-31 17:01 UTC (permalink / raw)
To: Michael Tokarev; +Cc: qemu-arm, qemu-devel, qemu-stable
On Thu, 31 Oct 2024 at 16:55, Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 29.10.2024 18:10, Peter Maydell wrote:
> ...
> > (Note for stable backports: the bug goes back to 4a15527c9fee but
> > this code was refactored in commits ea8618382aba..a8ab8706d4cc461, so
> > fixing it in branches without those refactorings will mean either
> > backporting the refactor or else implementing a conceptually similar
> > fix for the old code.)
>
> What do you think is the better way here -- pick up the refactoring
> changes (to 9.0 and earlier), do a backport of this single fix, or
> do nothing? Note for 7.2 branch it probably requires quite a bit
> more work.
The bug being fixed here is a bit niche (I don't think many
people build with KVM support only) so I would not worry
about backporting it all the way to 7.2. I'm not sure about
the best approach for 9.0 (which is why I left that note rather
than actively suggestion one or the other) -- it depends whether
you value more "backport the change that's actually been tested
by being in mainline" or "make the minimal set of changes in the
stable branch"...
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
2024-10-31 17:01 ` Peter Maydell
@ 2024-10-31 17:31 ` Michael Tokarev
2024-10-31 17:40 ` Peter Maydell
0 siblings, 1 reply; 25+ messages in thread
From: Michael Tokarev @ 2024-10-31 17:31 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, qemu-stable
31.10.2024 20:01, Peter Maydell wrote:
> On Thu, 31 Oct 2024 at 16:55, Michael Tokarev <mjt@tls.msk.ru> wrote:
>>
>> 29.10.2024 18:10, Peter Maydell wrote:
>> ...
>>> (Note for stable backports: the bug goes back to 4a15527c9fee but
>>> this code was refactored in commits ea8618382aba..a8ab8706d4cc461, so
>>> fixing it in branches without those refactorings will mean either
>>> backporting the refactor or else implementing a conceptually similar
>>> fix for the old code.)
>>
>> What do you think is the better way here -- pick up the refactoring
>> changes (to 9.0 and earlier), do a backport of this single fix, or
>> do nothing? Note for 7.2 branch it probably requires quite a bit
>> more work.
>
> The bug being fixed here is a bit niche (I don't think many
> people build with KVM support only) so I would not worry
> about backporting it all the way to 7.2. I'm not sure about
> the best approach for 9.0 (which is why I left that note rather
> than actively suggestion one or the other) -- it depends whether
> you value more "backport the change that's actually been tested
> by being in mainline" or "make the minimal set of changes in the
> stable branch"...
Aha.
Well.
What I see is that the whole thing - plus one more commit right
before the mentioned refactoring, ea8618382aba, "target/arm: Correct
comments about M-profile FPSCR" - applies cleanly to 9.0 and 8.2.
For 7.2 though, this is definitely too much because there, tcg code
has different rules for the temps, - in particular, it frees all
temps explicitly, so new code wont fit there anyway, resulting in
leaks and requiring major re-review.
Being niche, I'd not bother with that even in 8.2, but the fact
this refactoring applies nicely.. :)
It's probably the first time when the difference between many
changes but tested in master, vs smaller possible change, is quite
significant. I prefer for it to just work ;))
8.2 is in ubuntu noble (LTS), so it might be with us a bit longer
than some other series, but in ubuntu they build with KVM support,
so the bug isn't there.
For 7.2 there's no question anymore.
For 9.0, the next release will be the last one in the series
(unless something changes).
For being really niche, let's pick this single change to 9.1 only,
keeping other series without the fix, for now. Unless there are
other arguments to change this.
I especially thank you for the excellent summary in the patch itself!
/mjt
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
2024-10-31 17:31 ` Michael Tokarev
@ 2024-10-31 17:40 ` Peter Maydell
2024-10-31 17:44 ` Michael Tokarev
0 siblings, 1 reply; 25+ messages in thread
From: Peter Maydell @ 2024-10-31 17:40 UTC (permalink / raw)
To: Michael Tokarev; +Cc: qemu-arm, qemu-devel, qemu-stable
On Thu, 31 Oct 2024 at 17:31, Michael Tokarev <mjt@tls.msk.ru> wrote:
> What I see is that the whole thing - plus one more commit right
> before the mentioned refactoring, ea8618382aba, "target/arm: Correct
> comments about M-profile FPSCR" - applies cleanly to 9.0 and 8.2.
> For 7.2 though, this is definitely too much because there, tcg code
> has different rules for the temps, - in particular, it frees all
> temps explicitly, so new code wont fit there anyway, resulting in
> leaks and requiring major re-review.
>
> Being niche, I'd not bother with that even in 8.2, but the fact
> this refactoring applies nicely.. :)
>
> It's probably the first time when the difference between many
> changes but tested in master, vs smaller possible change, is quite
> significant. I prefer for it to just work ;))
>
> 8.2 is in ubuntu noble (LTS), so it might be with us a bit longer
> than some other series, but in ubuntu they build with KVM support,
> so the bug isn't there.
Note that the bug is not in "TCG + KVM" or "TCG only"
configs, but specifically "KVM without TCG" (i.e
you configured with '--disable-tcg' on an aarch64 host).
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
2024-10-31 17:40 ` Peter Maydell
@ 2024-10-31 17:44 ` Michael Tokarev
0 siblings, 0 replies; 25+ messages in thread
From: Michael Tokarev @ 2024-10-31 17:44 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, qemu-stable
31.10.2024 20:40, Peter Maydell:
>> 8.2 is in ubuntu noble (LTS), so it might be with us a bit longer
>> than some other series, but in ubuntu they build with KVM support,
>> so the bug isn't there.
>
> Note that the bug is not in "TCG + KVM" or "TCG only"
> configs, but specifically "KVM without TCG" (i.e
> you configured with '--disable-tcg' on an aarch64 host).
Yeah, what I meant is "they build with tcg *AND* KVM", -- they enable
KVM *too*", so the bug doesn't exist in their config, so we can ignore
ubuntu in this context.
Thanks,
/mjt
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PULL 04/18] target/arm: Don't assert in regime_is_user() for E10 mmuidx values
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2024-10-29 15:10 ` [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 05/18] hw/sd/omap_mmc: Don't use sd_cmd_type_t Peter Maydell
` (14 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
In regime_is_user() we assert if we're passed an ARMMMUIdx_E10_*
mmuidx value. This used to make sense because we only used this
function in ptw.c and would never use it on this kind of stage 1+2
mmuidx, only for an individual stage 1 or stage 2 mmuidx.
However, when we implemented FEAT_E0PD we added a callsite in
aa64_va_parameters(), which means this can now be called for
stage 1+2 mmuidx values if the guest sets the TCG_ELX.{E0PD0,E0PD1}
bits to enable use of the feature. This will then result in
an assertion failure later, for instance on a TLBI operation:
#6 0x00007ffff6d0e70f in g_assertion_message_expr
(domain=0x0, file=0x55555676eeba "../../target/arm/internals.h", line=978, func=0x555556771d48 <__func__.5> "regime_is_user", expr=<optimised out>)
at ../../../glib/gtestutils.c:3279
#7 0x0000555555f286d2 in regime_is_user (env=0x555557f2fe00, mmu_idx=ARMMMUIdx_E10_0) at ../../target/arm/internals.h:978
#8 0x0000555555f3e31c in aa64_va_parameters (env=0x555557f2fe00, va=18446744073709551615, mmu_idx=ARMMMUIdx_E10_0, data=true, el1_is_aa32=false)
at ../../target/arm/helper.c:12048
#9 0x0000555555f3163b in tlbi_aa64_get_range (env=0x555557f2fe00, mmuidx=ARMMMUIdx_E10_0, value=106721347371041) at ../../target/arm/helper.c:5214
#10 0x0000555555f317e8 in do_rvae_write (env=0x555557f2fe00, value=106721347371041, idxmap=21, synced=true) at ../../target/arm/helper.c:5260
#11 0x0000555555f31925 in tlbi_aa64_rvae1is_write (env=0x555557f2fe00, ri=0x555557fbeae0, value=106721347371041) at ../../target/arm/helper.c:5302
#12 0x0000555556036f8f in helper_set_cp_reg64 (env=0x555557f2fe00, rip=0x555557fbeae0, value=106721347371041) at ../../target/arm/tcg/op_helper.c:965
Since we do know whether these mmuidx values are for usermode
or not, we can easily make regime_is_user() handle them:
ARMMMUIdx_E10_0 is user, and the other two are not.
Cc: qemu-stable@nongnu.org
Fixes: e4c93e44ab103f ("target/arm: Implement FEAT_E0PD")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20241017172331.822587-1-peter.maydell@linaro.org
---
target/arm/internals.h | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 299a96a81a7..fd8f7c82aa3 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -963,6 +963,7 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
+ case ARMMMUIdx_E10_0:
case ARMMMUIdx_E20_0:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
@@ -972,10 +973,6 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
return true;
default:
return false;
- case ARMMMUIdx_E10_0:
- case ARMMMUIdx_E10_1:
- case ARMMMUIdx_E10_1_PAN:
- g_assert_not_reached();
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 05/18] hw/sd/omap_mmc: Don't use sd_cmd_type_t
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2024-10-29 15:10 ` [PULL 04/18] target/arm: Don't assert in regime_is_user() for E10 mmuidx values Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 06/18] tests/functional: Add a functional test for the collie board Peter Maydell
` (13 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
In commit 1ab08790bb75e4 we did some refactoring of the SD card
implementation, which included a rearrangement of the sd_cmd_type_t
enum values. Unfortunately we didn't notice that this enum is not
used solely inside the SD card model itself, but is also used by the
OMAP MMC controller device. In the OMAP MMC controller, it is used
to implement the handling of the Type field of the MMC_CMD register,
so changing the enum values so that they no longer lined up with the
bit definitions for that register field broke the controller model.
The effect is that Linux fails to boot from an SD card on the "sx1"
machine.
Give omap-mmc its own enum which we can document as needing to match
the encoding used in this device's register, so it isn't sharing
sd_cmd_type_t with the SD card model any more. We can then move
sd_cmd_type_t's definition out of sd.h and into sd.c, which is the
only place that uses it.
Cc: qemu-stable@nongnu.org
Fixes: 1ab08790bb75 ("hw/sd/sdcard: Store command type in SDProto")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20241017162755.710698-1-peter.maydell@linaro.org
---
include/hw/sd/sd.h | 8 --------
hw/sd/omap_mmc.c | 22 ++++++++++++++++------
hw/sd/sd.c | 8 ++++++++
3 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
index d35a839f5ef..f2458f37b3c 100644
--- a/include/hw/sd/sd.h
+++ b/include/hw/sd/sd.h
@@ -75,14 +75,6 @@ typedef enum {
UHS_III = 3, /* currently not supported */
} sd_uhs_mode_t;
-typedef enum {
- sd_spi,
- sd_bc, /* broadcast -- no response */
- sd_bcr, /* broadcast with response */
- sd_ac, /* addressed -- no data transfer */
- sd_adtc, /* addressed with data transfer */
-} sd_cmd_type_t;
-
typedef struct {
uint8_t cmd;
uint32_t arg;
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
index 91e9a3f1c6a..1d4e30e6b7b 100644
--- a/hw/sd/omap_mmc.c
+++ b/hw/sd/omap_mmc.c
@@ -103,6 +103,7 @@ static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
}
}
+/* These must match the encoding of the MMC_CMD Response field */
typedef enum {
sd_nore = 0, /* no response */
sd_r1, /* normal response command */
@@ -112,8 +113,17 @@ typedef enum {
sd_r1b = -1,
} sd_rsp_type_t;
+/* These must match the encoding of the MMC_CMD Type field */
+typedef enum {
+ SD_TYPE_BC = 0, /* broadcast -- no response */
+ SD_TYPE_BCR = 1, /* broadcast with response */
+ SD_TYPE_AC = 2, /* addressed -- no data transfer */
+ SD_TYPE_ADTC = 3, /* addressed with data transfer */
+} MMCCmdType;
+
static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
- sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
+ MMCCmdType type, int busy,
+ sd_rsp_type_t resptype, int init)
{
uint32_t rspstatus, mask;
int rsplen, timeout;
@@ -128,7 +138,7 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
if (resptype == sd_r1 && busy)
resptype = sd_r1b;
- if (type == sd_adtc) {
+ if (type == SD_TYPE_ADTC) {
host->fifo_start = 0;
host->fifo_len = 0;
host->transfer = 1;
@@ -433,10 +443,10 @@ static void omap_mmc_write(void *opaque, hwaddr offset,
for (i = 0; i < 8; i ++)
s->rsp[i] = 0x0000;
omap_mmc_command(s, value & 63, (value >> 15) & 1,
- (sd_cmd_type_t) ((value >> 12) & 3),
- (value >> 11) & 1,
- (sd_rsp_type_t) ((value >> 8) & 7),
- (value >> 7) & 1);
+ (MMCCmdType)((value >> 12) & 3),
+ (value >> 11) & 1,
+ (sd_rsp_type_t) ((value >> 8) & 7),
+ (value >> 7) & 1);
omap_mmc_update(s);
break;
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index a5d2d929a8a..b2e2d58e013 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -71,6 +71,14 @@ typedef enum {
sd_illegal = -2,
} sd_rsp_type_t;
+typedef enum {
+ sd_spi,
+ sd_bc, /* broadcast -- no response */
+ sd_bcr, /* broadcast with response */
+ sd_ac, /* addressed -- no data transfer */
+ sd_adtc, /* addressed with data transfer */
+} sd_cmd_type_t;
+
enum SDCardModes {
sd_inactive,
sd_card_identification_mode,
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 06/18] tests/functional: Add a functional test for the collie board
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2024-10-29 15:10 ` [PULL 05/18] hw/sd/omap_mmc: Don't use sd_cmd_type_t Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 07/18] tests/functional: Add a functional test for the sx1 board Peter Maydell
` (12 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Add a functional test for the collie board that uses the kernel and
rootfs provided by Guenter Roeck in the linux-test-downloads repo:
https://github.com/groeck/linux-test-downloads/
This just boots Linux with a userspace that immediately reboots
the board, so we wait for the reboot log line.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20241017163247.711244-2-peter.maydell@linaro.org
---
MAINTAINERS | 1 +
tests/functional/meson.build | 1 +
tests/functional/test_arm_collie.py | 31 +++++++++++++++++++++++++++++
3 files changed, 33 insertions(+)
create mode 100755 tests/functional/test_arm_collie.py
diff --git a/MAINTAINERS b/MAINTAINERS
index f48d9142b8a..6b1fa225d6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -929,6 +929,7 @@ F: hw/arm/strongarm*
F: hw/gpio/zaurus.c
F: include/hw/arm/sharpsl.h
F: docs/system/arm/collie.rst
+F: tests/functional/test_arm_collie.py
Stellaris
M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index 97c1c597e86..9538e103d6e 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -54,6 +54,7 @@ tests_alpha_system_thorough = [
tests_arm_system_thorough = [
'arm_aspeed',
'arm_canona1100',
+ 'arm_collie',
'arm_integratorcp',
'arm_raspi2',
'arm_vexpress',
diff --git a/tests/functional/test_arm_collie.py b/tests/functional/test_arm_collie.py
new file mode 100755
index 00000000000..7e144a0a8fb
--- /dev/null
+++ b/tests/functional/test_arm_collie.py
@@ -0,0 +1,31 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots a Linux kernel on a collie machine
+# and checks the console
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import LinuxKernelTest, Asset
+from qemu_test.utils import archive_extract
+
+class CollieTest(LinuxKernelTest):
+
+ ASSET_ZIMAGE = Asset(
+ 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/collie/zImage',
+ '10ace8abf9e0875ef8a83b8829cc3b5b50bc6d7bc3ca29f19f49f5673a43c13b')
+
+ ASSET_ROOTFS = Asset(
+ 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/collie/rootfs-sa110.cpio',
+ '89ccaaa5c6b33331887047e1618ffe81b0f55909173944347d5d2426f3bcc1f2')
+
+ def test_arm_collie(self):
+ self.set_machine('collie')
+ zimage_path = self.ASSET_ZIMAGE.fetch()
+ rootfs_path = self.ASSET_ROOTFS.fetch()
+ self.vm.add_args('-append', 'rdinit=/sbin/init console=ttySA1')
+ self.launch_kernel(zimage_path,
+ initrd=rootfs_path,
+ wait_for='reboot: Restarting system')
+
+if __name__ == '__main__':
+ LinuxKernelTest.main()
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 07/18] tests/functional: Add a functional test for the sx1 board
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2024-10-29 15:10 ` [PULL 06/18] tests/functional: Add a functional test for the collie board Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 08/18] scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing Peter Maydell
` (11 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Add a functional test for the sx1 board that uses the kernel and
rootfs provided by Guenter Roeck in the linux-test-downloads repo:
https://github.com/groeck/linux-test-downloads/
We have three variants of the test for this board:
* just boot initrd
* boot with filesystem on SD card
* boot from flash
In all cases these images have a userspace that is configured to
immediately reboot the system on successful boot, and the board
itself supports telling QEMU to do the reboot, so we only need to
wait for QEMU to exit (via -no-reboot).
Since there are three subtests, the test as a whole takes about
80s on my local machine. That's about the same as the aarch64_virt
test, so give it the same overall test timeout as that one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20241017163247.711244-3-peter.maydell@linaro.org
---
tests/functional/meson.build | 2 +
tests/functional/test_arm_sx1.py | 72 ++++++++++++++++++++++++++++++++
2 files changed, 74 insertions(+)
create mode 100755 tests/functional/test_arm_sx1.py
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index 9538e103d6e..84a07970d41 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -18,6 +18,7 @@ test_timeouts = {
'arm_aspeed' : 600,
'arm_raspi2' : 120,
'arm_tuxrun' : 120,
+ 'arm_sx1' : 360,
'mips_malta' : 120,
'netdev_ethtool' : 180,
'ppc_40p' : 240,
@@ -57,6 +58,7 @@ tests_arm_system_thorough = [
'arm_collie',
'arm_integratorcp',
'arm_raspi2',
+ 'arm_sx1',
'arm_vexpress',
'arm_tuxrun',
]
diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py
new file mode 100755
index 00000000000..2d86405831e
--- /dev/null
+++ b/tests/functional/test_arm_sx1.py
@@ -0,0 +1,72 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2024 Linaro Ltd.
+#
+# Functional test that boots a Linux kernel on an sx1 machine
+# and checks the console. We have three variants:
+# * just boot initrd
+# * boot with filesystem on SD card
+# * boot from flash
+# In all cases these images have a userspace that is configured
+# to immediately reboot the system on successful boot, so we
+# only need to wait for QEMU to exit (via -no-reboot).
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import LinuxKernelTest, Asset
+from qemu_test.utils import archive_extract
+
+class SX1Test(LinuxKernelTest):
+
+ ASSET_ZIMAGE = Asset(
+ 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/zImage',
+ 'a0271899a8dc2165f9e0adb2d0a57fc839ae3a469722ffc56c77e108a8887615')
+
+ ASSET_INITRD = Asset(
+ 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/rootfs-armv4.cpio',
+ '35b0721249821aa544cd85b85d3cb8901db4c6d128eed86ab261e5d9e37d58f8')
+
+ ASSET_SD_FS = Asset(
+ 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/rootfs-armv4.ext2',
+ 'c1db7f43ef92469ebc8605013728c8950e7608439f01d13678994f0ce101c3a8')
+
+ ASSET_FLASH = Asset(
+ 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/flash',
+ '17e6a2758fa38efd2666be0879d4751fd37d194f25168a8deede420df519b676')
+
+ CONSOLE_ARGS = 'console=ttyS0,115200 earlycon=uart8250,mmio32,0xfffb0000,115200n8'
+
+ def test_arm_sx1_initrd(self):
+ self.set_machine('sx1')
+ zimage_path = self.ASSET_ZIMAGE.fetch()
+ initrd_path = self.ASSET_INITRD.fetch()
+ self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}')
+ self.vm.add_args('-no-reboot')
+ self.launch_kernel(zimage_path,
+ initrd=initrd_path)
+ self.vm.wait()
+
+ def test_arm_sx1_sd(self):
+ self.set_machine('sx1')
+ zimage_path = self.ASSET_ZIMAGE.fetch()
+ sd_fs_path = self.ASSET_SD_FS.fetch()
+ self.vm.add_args('-append', f'kunit.enable=0 root=/dev/mmcblk0 rootwait {self.CONSOLE_ARGS}')
+ self.vm.add_args('-no-reboot')
+ self.vm.add_args('-snapshot')
+ self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}')
+ self.launch_kernel(zimage_path)
+ self.vm.wait()
+
+ def test_arm_sx1_flash(self):
+ self.set_machine('sx1')
+ zimage_path = self.ASSET_ZIMAGE.fetch()
+ flash_path = self.ASSET_FLASH.fetch()
+ self.vm.add_args('-append', f'kunit.enable=0 root=/dev/mtdblock3 rootwait {self.CONSOLE_ARGS}')
+ self.vm.add_args('-no-reboot')
+ self.vm.add_args('-snapshot')
+ self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}')
+ self.launch_kernel(zimage_path)
+ self.vm.wait()
+
+if __name__ == '__main__':
+ LinuxKernelTest.main()
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 08/18] scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2024-10-29 15:10 ` [PULL 07/18] tests/functional: Add a functional test for the sx1 board Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 09/18] docs/system/arm/stm32: List olimex-stm32-h405 in document title Peter Maydell
` (10 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
From: Akihiko Odaki <akihiko.odaki@daynix.com>
The arguments in MESONINTROSPECT are quoted with shlex.quote() so it
must be parsed with shlex.split(). Otherwise the script will fail if
the build directory has a character like "~" in it.
Note: this fix cannot be backported directly to any stable branch
that doesn't require Meson version 1.4.0 or better; otherwise it will
work OK on Linux but will break on Windows hosts.
(Unfortunately, Meson prior to version 1.4.0 was inconsistent between
host OSes about how it quoted arguments, and used a different quoting
process on Windows hosts. Our current git trunk already requires
1.5.0 as of commit 07f0d32641e ("Require meson version 1.5.0"), but
the stable branches are still on older Meson.)
Fixes: cf60ccc330 ("cutils: Introduce bundle mechanism")
Reported-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20241018130852.931509-1-peter.maydell@linaro.org
[PMM: Updated commit message to give all the detail about the
Meson version compability requirements.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
scripts/symlink-install-tree.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/symlink-install-tree.py b/scripts/symlink-install-tree.py
index 8ed97e3c943..b72563895c5 100644
--- a/scripts/symlink-install-tree.py
+++ b/scripts/symlink-install-tree.py
@@ -4,6 +4,7 @@
import errno
import json
import os
+import shlex
import subprocess
import sys
@@ -14,7 +15,7 @@ def destdir_join(d1: str, d2: str) -> str:
return str(PurePath(d1, *PurePath(d2).parts[1:]))
introspect = os.environ.get('MESONINTROSPECT')
-out = subprocess.run([*introspect.split(' '), '--installed'],
+out = subprocess.run([*shlex.split(introspect), '--installed'],
stdout=subprocess.PIPE, check=True).stdout
for source, dest in json.loads(out).items():
bundle_dest = destdir_join('qemu-bundle', dest)
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 09/18] docs/system/arm/stm32: List olimex-stm32-h405 in document title
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2024-10-29 15:10 ` [PULL 08/18] scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 10/18] docs/system/arm: Don't use wildcard '*-bmc' in doc titles Peter Maydell
` (9 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
List the olimex-stm32-h405 board in the document title, so that the
board name appears in the table of contents in system/target-arm.rst.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20241018141332.942844-2-peter.maydell@linaro.org
---
docs/system/arm/stm32.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
index ca7a55841b4..511e3eb9ac1 100644
--- a/docs/system/arm/stm32.rst
+++ b/docs/system/arm/stm32.rst
@@ -1,5 +1,5 @@
-STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
-========================================================================================
+STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vldiscovery``)
+===============================================================================================================
The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
STMicroelectronics.
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 10/18] docs/system/arm: Don't use wildcard '*-bmc' in doc titles
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2024-10-29 15:10 ` [PULL 09/18] docs/system/arm/stm32: List olimex-stm32-h405 in document title Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 11/18] docs/system/arm: Split fby35 out from aspeed.rst Peter Maydell
` (8 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
We have two Arm board doc files which both use '*-bmc' in their
documentation title. The result is that when you read the
table of contents in system/target-arm.html you don't know
which boards are covered by which file.
Expand out the board names entirely in the document titles.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20241018141332.942844-3-peter.maydell@linaro.org
---
docs/system/arm/aspeed.rst | 4 ++--
docs/system/arm/nuvoton.rst | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 6733ffd2b94..968ba88b997 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -1,5 +1,5 @@
-Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``)
-===================================================================================
+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
+========================================================================================================================================================================================================================================================================================================================================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
Aspeed evaluation boards. They are based on different releases of the
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index 0424cae4b01..05059378e55 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -1,5 +1,5 @@
-Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
-================================================================
+Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj``)
+=====================================================================================================
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
designed to be used as Baseboard Management Controllers (BMCs) in various
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 11/18] docs/system/arm: Split fby35 out from aspeed.rst
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2024-10-29 15:10 ` [PULL 10/18] docs/system/arm: Don't use wildcard '*-bmc' in doc titles Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 12/18] docs/system/arm: Add placeholder doc for exynos4 boards Peter Maydell
` (7 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
The fby35 machine is not implemented in hw/arm/aspeed.c,
but its documentation is currently stuck at the end of aspeed.rst,
formatted in a way that it gets its own heading in the top-level
list of boards in target-arm.html.
We don't have any other boards that we document like this; split it
out into its own rst file. This improves consistency with other
board docs and means we can have the entry in the target-arm
list be in the correct alphabetical order.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20241018141332.942844-4-peter.maydell@linaro.org
---
MAINTAINERS | 1 +
docs/system/arm/aspeed.rst | 48 --------------------------------------
docs/system/arm/fby35.rst | 47 +++++++++++++++++++++++++++++++++++++
docs/system/target-arm.rst | 1 +
4 files changed, 49 insertions(+), 48 deletions(-)
create mode 100644 docs/system/arm/fby35.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index 6b1fa225d6e..e74d16bcf1d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1123,6 +1123,7 @@ F: include/hw/*/*aspeed*
F: hw/net/ftgmac100.c
F: include/hw/net/ftgmac100.h
F: docs/system/arm/aspeed.rst
+F: docs/system/arm/fby35.rst
F: tests/*/*aspeed*
F: tests/*/*ast2700*
F: hw/arm/fby35.c
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 968ba88b997..63910d382fe 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -257,51 +257,3 @@ To boot a kernel directly from a Zephyr build tree:
$ qemu-system-arm -M ast1030-evb -nographic \
-kernel zephyr.elf
-
-Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``)
-==================================================================
-
-Facebook has a series of multi-node compute server designs named
-Yosemite. The most recent version released was
-`Yosemite v3 <https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf>`__.
-
-Yosemite v3.5 is an iteration on this design, and is very similar: there's a
-baseboard with a BMC, and 4 server slots. The new server board design termed
-"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to
-include various compute accelerators (video, inferencing, etc). At the moment,
-only the first server slot's BIC is included.
-
-Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
-can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
-for an example.
-
-In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
-runs `OpenBMC <https://github.com/facebook/openbmc>`__, and the BIC runs
-`OpenBIC <https://github.com/facebook/openbic>`__.
-
-Firmware images can be retrieved from the Github releases or built from the
-source code, see the README's for instructions on that. This image uses the
-"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC.
-Some reference images can also be found here:
-
-.. code-block:: bash
-
- $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
- $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
-
-Since this machine has multiple SoC's, each with their own serial console, the
-recommended way to run it is to allocate a pseudoterminal for each serial
-console and let the monitor use stdio. Also, starting in a paused state is
-useful because it allows you to attach to the pseudoterminals before the boot
-process starts.
-
-.. code-block:: bash
-
- $ qemu-system-arm -machine fby35 \
- -drive file=fby35.mtd,format=raw,if=mtd \
- -device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \
- -serial pty -serial pty -serial mon:stdio \
- -display none -S
- $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc.
- $ screen /dev/tty1
- $ (qemu) c # Start the boot process once screen is setup.
diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
new file mode 100644
index 00000000000..742b887d44c
--- /dev/null
+++ b/docs/system/arm/fby35.rst
@@ -0,0 +1,47 @@
+Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``)
+==================================================================
+
+Facebook has a series of multi-node compute server designs named
+Yosemite. The most recent version released was
+`Yosemite v3 <https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf>`__.
+
+Yosemite v3.5 is an iteration on this design, and is very similar: there's a
+baseboard with a BMC, and 4 server slots. The new server board design termed
+"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to
+include various compute accelerators (video, inferencing, etc). At the moment,
+only the first server slot's BIC is included.
+
+Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
+can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
+for an example.
+
+In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
+runs `OpenBMC <https://github.com/facebook/openbmc>`__, and the BIC runs
+`OpenBIC <https://github.com/facebook/openbic>`__.
+
+Firmware images can be retrieved from the Github releases or built from the
+source code, see the README's for instructions on that. This image uses the
+"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC.
+Some reference images can also be found here:
+
+.. code-block:: bash
+
+ $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
+ $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
+
+Since this machine has multiple SoC's, each with their own serial console, the
+recommended way to run it is to allocate a pseudoterminal for each serial
+console and let the monitor use stdio. Also, starting in a paused state is
+useful because it allows you to attach to the pseudoterminals before the boot
+process starts.
+
+.. code-block:: bash
+
+ $ qemu-system-arm -machine fby35 \
+ -drive file=fby35.mtd,format=raw,if=mtd \
+ -device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \
+ -serial pty -serial pty -serial mon:stdio \
+ -display none -S
+ $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc.
+ $ screen /dev/tty1
+ $ (qemu) c # Start the boot process once screen is setup.
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index 3c0a5848453..9c01e66ffa9 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -90,6 +90,7 @@ undocumented; you can get a complete list by running
arm/digic
arm/cubieboard
arm/emcraft-sf2
+ arm/fby35
arm/musicpal
arm/kzm
arm/nrf
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 12/18] docs/system/arm: Add placeholder doc for exynos4 boards
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2024-10-29 15:10 ` [PULL 11/18] docs/system/arm: Split fby35 out from aspeed.rst Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 13/18] docs/system/arm: Add placeholder doc for xlnx-zcu102 board Peter Maydell
` (6 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Add a placeholder doc for the exynos4 boards nuri and smdkc210.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20241018141332.942844-5-peter.maydell@linaro.org
---
MAINTAINERS | 1 +
docs/system/arm/exynos.rst | 9 +++++++++
docs/system/target-arm.rst | 1 +
3 files changed, 11 insertions(+)
create mode 100644 docs/system/arm/exynos.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index e74d16bcf1d..2b524d7af54 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -716,6 +716,7 @@ L: qemu-arm@nongnu.org
S: Odd Fixes
F: hw/*/exynos*
F: include/hw/*/exynos*
+F: docs/system/arm/exynos.rst
Calxeda Highbank
M: Rob Herring <robh@kernel.org>
diff --git a/docs/system/arm/exynos.rst b/docs/system/arm/exynos.rst
new file mode 100644
index 00000000000..86894bc02b7
--- /dev/null
+++ b/docs/system/arm/exynos.rst
@@ -0,0 +1,9 @@
+Exynos4 boards (``nuri``, ``smdkc210``)
+=======================================
+
+These are machines which use the Samsung Exynos4210 SoC, which has Cortex-A9 CPUs.
+
+``nuri`` models the Samsung NURI board.
+
+``smdkc210`` models the Samsung SMDKC210 board.
+
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index 9c01e66ffa9..a7f88c8f317 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -90,6 +90,7 @@ undocumented; you can get a complete list by running
arm/digic
arm/cubieboard
arm/emcraft-sf2
+ arm/exynos
arm/fby35
arm/musicpal
arm/kzm
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 13/18] docs/system/arm: Add placeholder doc for xlnx-zcu102 board
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2024-10-29 15:10 ` [PULL 12/18] docs/system/arm: Add placeholder doc for exynos4 boards Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 14/18] docs/system/arm: Add placeholder docs for mcimx6ul-evk and mcimx7d-sabre Peter Maydell
` (5 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Add a placeholder doc for the xlnx-zcu102 board.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20241018141332.942844-6-peter.maydell@linaro.org
---
MAINTAINERS | 1 +
docs/system/arm/xlnx-zcu102.rst | 19 +++++++++++++++++++
docs/system/target-arm.rst | 1 +
3 files changed, 21 insertions(+)
create mode 100644 docs/system/arm/xlnx-zcu102.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index 2b524d7af54..66c7572c27b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1018,6 +1018,7 @@ F: include/hw/ssi/xilinx_spips.h
F: hw/display/dpcd.c
F: include/hw/display/dpcd.h
F: docs/system/arm/xlnx-versal-virt.rst
+F: docs/system/arm/xlnx-zcu102.rst
Xilinx Versal OSPI
M: Francisco Iglesias <francisco.iglesias@amd.com>
diff --git a/docs/system/arm/xlnx-zcu102.rst b/docs/system/arm/xlnx-zcu102.rst
new file mode 100644
index 00000000000..534cd1dc887
--- /dev/null
+++ b/docs/system/arm/xlnx-zcu102.rst
@@ -0,0 +1,19 @@
+Xilinx ZynqMP ZCU102 (``xlnx-zcu102``)
+======================================
+
+The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board.
+This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs.
+
+Machine-specific options
+""""""""""""""""""""""""
+
+The following machine-specific options are supported:
+
+secure
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
+ Arm Security Extensions (TrustZone). The default is ``off``.
+
+virtualization
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
+ Arm Virtualization Extensions. The default is ``off``.
+
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index a7f88c8f317..ace36d1b17d 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -107,6 +107,7 @@ undocumented; you can get a complete list by running
arm/xenpvh
arm/xlnx-versal-virt
arm/xlnx-zynq
+ arm/xlnx-zcu102
Emulated CPU architecture support
=================================
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 14/18] docs/system/arm: Add placeholder docs for mcimx6ul-evk and mcimx7d-sabre
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2024-10-29 15:10 ` [PULL 13/18] docs/system/arm: Add placeholder doc for xlnx-zcu102 board Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 15/18] docs/system/target-arm.rst: Remove "many boards are undocumented" note Peter Maydell
` (4 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Add placeholder docs for the mcimx6ul-evk and mcimx7d-sabre boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20241018141332.942844-7-peter.maydell@linaro.org
---
MAINTAINERS | 2 ++
docs/system/arm/mcimx6ul-evk.rst | 5 +++++
docs/system/arm/mcimx7d-sabre.rst | 5 +++++
docs/system/target-arm.rst | 2 ++
4 files changed, 14 insertions(+)
create mode 100644 docs/system/arm/mcimx6ul-evk.rst
create mode 100644 docs/system/arm/mcimx7d-sabre.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index 66c7572c27b..1e88b5738cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -791,6 +791,7 @@ F: hw/arm/fsl-imx6ul.c
F: hw/misc/imx6ul_ccm.c
F: include/hw/arm/fsl-imx6ul.h
F: include/hw/misc/imx6ul_ccm.h
+F: docs/system/arm/mcimx6ul-evk.rst
MCIMX7D SABRE / i.MX7
M: Peter Maydell <peter.maydell@linaro.org>
@@ -804,6 +805,7 @@ F: include/hw/arm/fsl-imx7.h
F: include/hw/misc/imx7_*.h
F: hw/pci-host/designware.c
F: include/hw/pci-host/designware.h
+F: docs/system/arm/mcimx7d-sabre.rst
MPS2 / MPS3
M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/docs/system/arm/mcimx6ul-evk.rst b/docs/system/arm/mcimx6ul-evk.rst
new file mode 100644
index 00000000000..8871138ab3e
--- /dev/null
+++ b/docs/system/arm/mcimx6ul-evk.rst
@@ -0,0 +1,5 @@
+NXP MCIMX6UL-EVK (``mcimx6ul-evk``)
+===================================
+
+The ``mcimx6ul-evk`` machine models the NXP i.MX6UltraLite Evaluation Kit
+MCIMX6UL-EVK development board. It has a single Cortex-A7 CPU.
diff --git a/docs/system/arm/mcimx7d-sabre.rst b/docs/system/arm/mcimx7d-sabre.rst
new file mode 100644
index 00000000000..c5d35af1d44
--- /dev/null
+++ b/docs/system/arm/mcimx7d-sabre.rst
@@ -0,0 +1,5 @@
+NXP MCIMX7D Sabre (``mcimx7d-sabre``)
+=====================================
+
+The ``mcimx7d-sabre`` machine models the NXP SABRE Board MCIMX7SABRE,
+based an an i.MX7Dual SoC.
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index ace36d1b17d..1f806cf4a46 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -97,6 +97,8 @@ undocumented; you can get a complete list by running
arm/nrf
arm/nuvoton
arm/imx25-pdk
+ arm/mcimx6ul-evk
+ arm/mcimx7d-sabre
arm/orangepi
arm/raspi
arm/collie
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 15/18] docs/system/target-arm.rst: Remove "many boards are undocumented" note
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2024-10-29 15:10 ` [PULL 14/18] docs/system/arm: Add placeholder docs for mcimx6ul-evk and mcimx7d-sabre Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 16/18] target/arm: Fix arithmetic underflow in SETM instruction Peter Maydell
` (3 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
We now have at least placeholder documentation for every Arm board,
so we can remove the apologetic note that says that there are
undocumented ones which you can only find out about via the
``--machine help`` option.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20241018141332.942844-8-peter.maydell@linaro.org
---
docs/system/target-arm.rst | 4 ----
1 file changed, 4 deletions(-)
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index 1f806cf4a46..9aaa9c414c9 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -63,10 +63,6 @@ large amounts of RAM. It also supports 64-bit CPUs.
Board-specific documentation
============================
-Unfortunately many of the Arm boards QEMU supports are currently
-undocumented; you can get a complete list by running
-``qemu-system-aarch64 --machine help``.
-
..
This table of contents should be kept sorted alphabetically
by the title text of each file, which isn't the same ordering
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 16/18] target/arm: Fix arithmetic underflow in SETM instruction
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2024-10-29 15:10 ` [PULL 15/18] docs/system/target-arm.rst: Remove "many boards are undocumented" note Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 17/18] docs/devel/reset: Fix minor grammatical error Peter Maydell
` (2 subsequent siblings)
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
From: Ido Plat <ido.plat1@ibm.com>
Pass the stage size to step function callback, otherwise do_setm
would hang when size is larger then page size because stage size
would underflow. This fix changes do_setm to be more inline with
do_setp.
Cc: qemu-stable@nongnu.org
Fixes: 0e92818887dee ("target/arm: Implement the SET* instructions")
Signed-off-by: Ido Plat <ido.plat1@ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025024909.799989-1-ido.plat1@ibm.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/helper-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 56b431faf57..8f42a28d07b 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -1348,7 +1348,7 @@ static void do_setm(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc,
/* Do the actual memset: we leave the last partial page to SETE */
stagesetsize = setsize & TARGET_PAGE_MASK;
while (stagesetsize > 0) {
- step = stepfn(env, toaddr, setsize, data, memidx, &mtedesc, ra);
+ step = stepfn(env, toaddr, stagesetsize, data, memidx, &mtedesc, ra);
toaddr += step;
setsize -= step;
stagesetsize -= step;
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 17/18] docs/devel/reset: Fix minor grammatical error
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2024-10-29 15:10 ` [PULL 16/18] target/arm: Fix arithmetic underflow in SETM instruction Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-29 15:10 ` [PULL 18/18] target/arm: kvm: require KVM_CAP_DEVICE_CTRL Peter Maydell
2024-10-31 16:33 ` [PULL 00/18] target-arm queue Peter Maydell
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Fix a minor grammatical error in the reset documentation:
a couple of missing words and a singular/plural swap.
Signed-off-by: Axel Heider <axel.heider@codasip.com>
Message-id: 173006362760.28451.11319467059840843945-1@git.sr.ht
[PMM: squashed two patches into one, tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/devel/reset.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst
index 74c7c0171ad..adefd59ef97 100644
--- a/docs/devel/reset.rst
+++ b/docs/devel/reset.rst
@@ -286,8 +286,8 @@ every reset child of the given resettable object. All children must be
resettable too. Additional parameters (a reset type and an opaque pointer) must
be passed to the callback too.
-In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located
-``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented
+In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located in the
+``DeviceState`` and ``BusState`` structures. ``child_foreach()`` is implemented
to follow the bus hierarchy; for a bus, it calls the function on every child
device; for a device, it calls the function on every bus child. When we reset
the main system bus, we reset the whole machine bus tree.
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PULL 18/18] target/arm: kvm: require KVM_CAP_DEVICE_CTRL
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2024-10-29 15:10 ` [PULL 17/18] docs/devel/reset: Fix minor grammatical error Peter Maydell
@ 2024-10-29 15:10 ` Peter Maydell
2024-10-31 16:33 ` [PULL 00/18] target-arm queue Peter Maydell
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-29 15:10 UTC (permalink / raw)
To: qemu-arm, qemu-devel
From: Paolo Bonzini <pbonzini@redhat.com>
The device control API was added in 2013, assume that it is present.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20241024113126.44343-1-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/kvm_arm.h | 16 +++++++---------
hw/intc/arm_gic_kvm.c | 9 +--------
target/arm/kvm.c | 17 +++++------------
3 files changed, 13 insertions(+), 29 deletions(-)
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 4d293618a78..2e6b49bf137 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -22,17 +22,15 @@
* @devid: the KVM device ID
* @group: device control API group for setting addresses
* @attr: device control API address type
- * @dev_fd: device control device file descriptor (or -1 if not supported)
+ * @dev_fd: device control device file descriptor
* @addr_ormask: value to be OR'ed with resolved address
*
- * Remember the memory region @mr, and when it is mapped by the
- * machine model, tell the kernel that base address using the
- * KVM_ARM_SET_DEVICE_ADDRESS ioctl or the newer device control API. @devid
- * should be the ID of the device as defined by KVM_ARM_SET_DEVICE_ADDRESS or
- * the arm-vgic device in the device control API.
- * The machine model may map
- * and unmap the device multiple times; the kernel will only be told the final
- * address at the point where machine init is complete.
+ * Remember the memory region @mr, and when it is mapped by the machine
+ * model, tell the kernel that base address using the device control API.
+ * @devid should be the ID of the device as defined by the arm-vgic device
+ * in the device control API. The machine model may map and unmap the device
+ * multiple times; the kernel will only be told the final address at the
+ * point where machine init is complete.
*/
void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
uint64_t attr, int dev_fd, uint64_t addr_ormask);
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 53defee7d59..e2a73337b1e 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -547,17 +547,10 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
&error_abort);
}
- } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) {
+ } else {
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
error_append_hint(errp,
"Perhaps the host CPU does not support GICv2?\n");
- } else if (ret != -ENODEV && ret != -ENOTSUP) {
- /*
- * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
- * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE",
- * and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
- */
- error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
return;
}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 000afa03631..7b6812c0de2 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -42,6 +42,7 @@
#include "migration/blocker.h"
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+ KVM_CAP_INFO(DEVICE_CTRL),
KVM_CAP_LAST_INFO
};
@@ -691,19 +692,11 @@ static void kvm_arm_set_device_addr(KVMDevice *kd)
{
struct kvm_device_attr *attr = &kd->kdattr;
int ret;
+ uint64_t addr = kd->kda.addr;
- /* If the device control API is available and we have a device fd on the
- * KVMDevice struct, let's use the newer API
- */
- if (kd->dev_fd >= 0) {
- uint64_t addr = kd->kda.addr;
-
- addr |= kd->kda_addr_ormask;
- attr->addr = (uintptr_t)&addr;
- ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
- } else {
- ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda);
- }
+ addr |= kd->kda_addr_ormask;
+ attr->addr = (uintptr_t)&addr;
+ ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
if (ret < 0) {
fprintf(stderr, "Failed to set device address: %s\n",
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PULL 00/18] target-arm queue
2024-10-29 15:10 [PULL 00/18] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2024-10-29 15:10 ` [PULL 18/18] target/arm: kvm: require KVM_CAP_DEVICE_CTRL Peter Maydell
@ 2024-10-31 16:33 ` Peter Maydell
18 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2024-10-31 16:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
On Tue, 29 Oct 2024 at 15:10, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit fdf250e5a37830615e324017cb3a503e84b3712c:
>
> Merge tag 'pull-maintainer-oct-misc-241024-1' of https://gitlab.com/stsquad/qemu into staging (2024-10-25 19:12:06 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241029
>
> for you to fetch changes up to 84f298ea3e2f0627c09871561e55068db9ff9180:
>
> target/arm: kvm: require KVM_CAP_DEVICE_CTRL (2024-10-29 15:04:47 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * arm/kvm: add support for MTE
> * docs/system/cpu-hotplug: Update example's socket-id/core-id
> * target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr
> * target/arm: Don't assert in regime_is_user() for E10 mmuidx values
> * hw/sd/omap_mmc: Fix breakage of OMAP MMC controller
> * tests/functional: Add functional tests for collie, sx1
> * scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing
> * docs/system/arm: Document remaining undocumented boards
> * target/arm: Fix arithmetic underflow in SETM instruction
> * docs/devel/reset: Fix minor grammatical error
> * target/arm: kvm: require KVM_CAP_DEVICE_CTRL
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread