From: Peter Maydell <peter.maydell@linaro.org>
To: Don Slutz <Don@cloudswitch.com>
Cc: Alex ZUEPKE <azuepke@sysgo.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] x86: enforce DPL checking on task gate switches invoked through IDT
Date: Fri, 31 Aug 2012 18:01:58 +0100 [thread overview]
Message-ID: <CAFEAcA8ZAk1FaGRQMBrmOdn4CSOWArMcUvrcqde0GHLV=mp9Cg@mail.gmail.com> (raw)
In-Reply-To: <5040EC40.90003@CloudSwitch.Com>
On 31 August 2012 17:54, Don Slutz <Don@cloudswitch.com> wrote:
> I think it makes sense to move the next 2 checks into the switch (no real
> code flow change).
I agree (for symmetry). If you do that then I think the
combination of those two patches means that in the task
gate case we do the !(e2 & DESC_P_MASK) check first and
then the dpl<cpl check; whereas in the other cases we
do them the other way around. Is that actually correct
behaviour? If so I think it probably deserves a comment
(perhaps just a clarification/expansion of the one currently
in the 'case 5' code) to the effect that the error
handling on the task gate case is genuinely different.
-- PMM
next prev parent reply other threads:[~2012-08-31 17:02 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-17 15:30 [Qemu-devel] [PATCH] x86: enforce DPL checking on task gate switches invoked through IDT Alex ZUEPKE
2012-08-27 16:39 ` Alex ZUEPKE
2012-08-31 16:54 ` Don Slutz
2012-08-31 17:01 ` Peter Maydell [this message]
2012-09-01 11:42 ` Blue Swirl
-- strict thread matches above, loose matches on Subject: below --
2012-08-17 9:14 Alex ZUEPKE
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