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Date: Fri, 31 Aug 2012 18:01:58 +0100
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From: Peter Maydell <peter.maydell@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH] x86: enforce DPL checking on task gate
 switches invoked through IDT
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To: Don Slutz <Don@cloudswitch.com>
Cc: Alex ZUEPKE <azuepke@sysgo.com>, qemu-devel@nongnu.org

On 31 August 2012 17:54, Don Slutz <Don@cloudswitch.com> wrote:
> I think it makes sense to move the next 2 checks into the switch (no real
> code flow change).

I agree (for symmetry). If you do that then I think the
combination of those two patches means that in the task
gate case we do the !(e2 & DESC_P_MASK) check first and
then the dpl<cpl check; whereas in the other cases we
do them the other way around. Is that actually correct
behaviour? If so I think it probably deserves a comment
(perhaps just a clarification/expansion of the one currently
in the 'case 5' code) to the effect that the error
handling on the task gate case is genuinely different.

-- PMM