From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43696) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3SJu-0007gc-9D for qemu-devel@nongnu.org; Fri, 12 Jun 2015 13:00:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z3SJo-0007pd-Ty for qemu-devel@nongnu.org; Fri, 12 Jun 2015 13:00:42 -0400 Received: from mail-vn0-f43.google.com ([209.85.216.43]:46192) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3SJo-0007pZ-Pz for qemu-devel@nongnu.org; Fri, 12 Jun 2015 13:00:36 -0400 Received: by vnbf7 with SMTP id f7so6944716vnb.13 for ; Fri, 12 Jun 2015 10:00:36 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1433500421-22879-5-git-send-email-edgar.iglesias@gmail.com> References: <1433500421-22879-1-git-send-email-edgar.iglesias@gmail.com> <1433500421-22879-5-git-send-email-edgar.iglesias@gmail.com> From: Peter Maydell Date: Fri, 12 Jun 2015 18:00:15 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v4 4/6] target-arm: Add the Hypervisor timer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: Edgar Iglesias , Sergey Fedorov , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Alexander Graf On 5 June 2015 at 11:33, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > static const ARMCPRegInfo generic_timer_cp_reginfo[] = { > /* Note that CNTFRQ is purely reads-as-written for the benefit > * of software; writing it doesn't actually change the timer frequency. > @@ -2648,6 +2683,18 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, > .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, > .resetvalue = 0 }, > + { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, > + .access = PL2_RW, > + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, }, > + { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, > + .access = PL2_RW, > + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, }, > + { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, > + .access = PL2_RW, > + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, }, raz/wi should be implemented as ARM_CP_CONST... Consider ordering these three defs CVAL, TVAL, CTL, so they're in the natural order by opc2? (Ditto below.) Can we have the AArch32 bindings too, please? > REGINFO_SENTINEL > }; > > @@ -2774,6 +2821,23 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, > .writefn = gt_cntvoff_write, > .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, > + { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_IO, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), > + .resetvalue = 0, > + .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, > + { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, > + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), > + .type = ARM_CP_IO, .access = PL2_RW, > + .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, > + { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, > + .type = ARM_CP_IO, .access = PL2_RW, > + .resetfn = gt_hyp_cnt_reset, > + .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, > #endif > REGINFO_SENTINEL > }; -- PMM