From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Alistair Francis <alistair23@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL v2 00/19] riscv-to-apply queue
Date: Fri, 5 Mar 2021 15:15:12 +0000 [thread overview]
Message-ID: <CAFEAcA8bBzmaKmFTv-SZJa-wtPfcDh6a5uG7GwPxd_tOW_huhQ@mail.gmail.com> (raw)
In-Reply-To: <20210304144651.310037-1-alistair.francis@wdc.com>
On Thu, 4 Mar 2021 at 14:47, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit cb90ecf9349198558569f6c86c4c27d215406095:
>
> Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210304' into staging (2021-03-04 10:42:46 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210304
>
> for you to fetch changes up to 19800265d407f09f333cf80dba3e975eb7bc1872:
>
> hw/riscv: virt: Map high mmio for PCIe (2021-03-04 09:43:29 -0500)
>
> ----------------------------------------------------------------
> RISC-V PR for 6.0
>
> This PR is a collection of RISC-V patches:
> - Improvements to SiFive U OTP
> - Upgrade OpenSBI to v0.9
> - Support the QMP dump-guest-memory
> - Add support for the SiFive SPI controller (sifive_u)
> - Initial RISC-V system documentation
> - A fix for the Goldfish RTC
> - MAINTAINERS updates
> - Support for high PCIe memory in the virt machine
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
next prev parent reply other threads:[~2021-03-05 15:25 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-04 14:46 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2021-03-04 14:46 ` [PULL v2 01/19] target/riscv: Declare csr_ops[] with a known size Alistair Francis
2021-03-04 14:46 ` [PULL v2 02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails Alistair Francis
2021-03-04 14:46 ` [PULL v2 03/19] roms/opensbi: Upgrade from v0.8 to v0.9 Alistair Francis
2021-03-09 16:51 ` Philippe Mathieu-Daudé
2021-03-11 15:48 ` Alistair Francis
2021-03-04 14:46 ` [PULL v2 04/19] target-riscv: support QMP dump-guest-memory Alistair Francis
2021-03-04 14:46 ` [PULL v2 05/19] hw/block: m25p80: Add ISSI SPI flash support Alistair Francis
2021-03-04 14:46 ` [PULL v2 06/19] hw/block: m25p80: Add various ISSI flash information Alistair Francis
2021-03-04 14:46 ` [PULL v2 07/19] hw/ssi: Add SiFive SPI controller support Alistair Francis
2021-03-04 14:46 ` [PULL v2 08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Alistair Francis
2021-03-04 14:46 ` [PULL v2 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Alistair Francis
2021-03-04 14:46 ` [PULL v2 10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Alistair Francis
2021-03-04 14:46 ` [PULL v2 11/19] docs/system: Sort targets in alphabetical order Alistair Francis
2021-03-04 14:46 ` [PULL v2 12/19] docs/system: Add RISC-V documentation Alistair Francis
2021-03-04 14:46 ` [PULL v2 13/19] docs/system: riscv: Add documentation for sifive_u machine Alistair Francis
2021-03-04 14:46 ` [PULL v2 14/19] goldfish_rtc: re-arm the alarm after migration Alistair Francis
2021-03-04 14:46 ` [PULL v2 15/19] MAINTAINERS: Add a SiFive machine section Alistair Francis
2021-03-04 14:46 ` [PULL v2 16/19] hw/riscv: Drop 'struct MemmapEntry' Alistair Francis
2021-03-04 14:46 ` [PULL v2 17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Alistair Francis
2021-03-04 14:46 ` [PULL v2 18/19] hw/riscv: virt: Limit RAM size in a 32-bit system Alistair Francis
2021-03-04 14:46 ` [PULL v2 19/19] hw/riscv: virt: Map high mmio for PCIe Alistair Francis
2021-03-05 15:15 ` Peter Maydell [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-07-03 0:12 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2022-07-03 4:38 ` Richard Henderson
2020-11-03 15:21 Alistair Francis
2020-11-03 21:07 ` Peter Maydell
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