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From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 2 Nov 2018 14:37:51 +0000
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Subject: Re: [Qemu-devel] [PATCH 2/5] target/arm: Fill in ARMISARegisters
 for kvm64
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On 29 October 2018 at 16:03, Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 10/29/18 2:58 PM, Peter Maydell wrote:
>> I think I would prefer it if we expanded the id_isar* fields
>> in the ARMISARegisters struct to uint64_t. If you dislike
>> that, I think we should make this code fail a bit more gracefully
>> in the presence of an unexpected extension into the high bits
>> of these registers. Or just ignore the high bits, since we're
>> effectively trusting that future architecture versions use
>> a compatible meaning for these registers anyway.
>
> Given these options, I'd prefer to just ignore the high bits.
> I'm fairly comfortable trusting that the architecture gods
> won't mess up and assign values in there.  Otherwise they
> would have already expanded instead of adding ID_ISAR6.

OK with me.

I think we could also add a comment noting that if the host
CPU doesn't have AArch32 then the AArch32 sysregs still exist
to be read, but they return UNKNOWN values.

thanks
-- PMM