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From: Peter Maydell <peter.maydell@linaro.org>
To: Andrew Jones <drjones@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	Eric Auger <eric.auger@linaro.org>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>,
	Bogdan Purcareata <bogdan.purcareata@nxp.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Alexander Graf <agraf@suse.de>,
	G Gregory <graeme.gregory@linaro.org>
Subject: Re: [Qemu-devel] [PATCH] hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT
Date: Fri, 1 Jul 2016 14:31:35 +0100	[thread overview]
Message-ID: <CAFEAcA8bSu4pjE5rfFzMNx7S0CfTSnaqmw9YLbWVK4ufzPP+1w@mail.gmail.com> (raw)
In-Reply-To: <20160701114006.w7cjhvfnj5cg3ks7@hawk.localdomain>

On 1 July 2016 at 12:40, Andrew Jones <drjones@redhat.com> wrote:
> I might have mentioned in the commit message that the ACPI generation
> already does this, as _CCA is set to 1, added with commit bc64b96c
> (assuming I'm right, and a value of 1 there is the ACPI equivalent of
>  this patch)
>
> bc64b96c's commit message is also lacking, in the fact it doesn't
> state why the value of 1 is chosen, only that the attribute is
> compulsory, which I presume could have been added with the value 0
> to satisfy that.
>
> Anyway, I just wanted to point out that I *think* we're fine for
> ACPI. Perhaps I'm the only one who didn't know that already though...

Thanks for the update: I've edited the commit message to add:
# This brings the DT description into line with the ACPI description,
# which already marks the PCI bridge as cache coherent (see commit
# bc64b96c984abf).

thanks
-- PMM

      parent reply	other threads:[~2016-07-01 13:31 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-28 17:14 [Qemu-devel] [PATCH] hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT Ard Biesheuvel
2016-06-30 14:09 ` Peter Maydell
2016-07-01 11:40   ` Andrew Jones
2016-07-01 13:07     ` Ard Biesheuvel
2016-07-01 13:31     ` Peter Maydell [this message]

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