* [risu PATCH 1/5] loongarch: Add LSX instructions
2023-10-25 9:29 [risu PATCH 0/5] Add LoongArch LSX/LASX instructions Song Gao
@ 2023-10-25 9:29 ` Song Gao
2023-10-25 9:29 ` [risu PATCH 2/5] loongarch: Add LASX instructions Song Gao
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Song Gao @ 2023-10-25 9:29 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
loongarch64.risu | 807 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 807 insertions(+)
diff --git a/loongarch64.risu b/loongarch64.risu
index d625a12..78ccee3 100644
--- a/loongarch64.risu
+++ b/loongarch64.risu
@@ -610,3 +610,810 @@ fstx_s LA64 0011 10000011 10000 rk:5 rj:5 fd:5 \
fstx_d LA64 0011 10000011 11000 rk:5 rj:5 fd:5 \
!constraints { $rj != 0 && $rj != $rk && $rk != 2 && $rj != 2; } \
!memory { reg_plus_reg($rj, $rk); }
+
+#
+# LSX instructions
+#
+
+vadd_b LSX 0111 00000000 10100 vk:5 vj:5 vd:5
+vadd_h LSX 0111 00000000 10101 vk:5 vj:5 vd:5
+vadd_w LSX 0111 00000000 10110 vk:5 vj:5 vd:5
+vadd_d LSX 0111 00000000 10111 vk:5 vj:5 vd:5
+vadd_q LSX 0111 00010010 11010 vk:5 vj:5 vd:5
+vsub_b LSX 0111 00000000 11000 vk:5 vj:5 vd:5
+vsub_h LSX 0111 00000000 11001 vk:5 vj:5 vd:5
+vsub_w LSX 0111 00000000 11010 vk:5 vj:5 vd:5
+vsub_d LSX 0111 00000000 11011 vk:5 vj:5 vd:5
+vsub_q LSX 0111 00010010 11011 vk:5 vj:5 vd:5
+
+vaddi_bu LSX 0111 00101000 10100 imm:5 vj:5 vd:5
+vaddi_hu LSX 0111 00101000 10101 imm:5 vj:5 vd:5
+vaddi_wu LSX 0111 00101000 10110 imm:5 vj:5 vd:5
+vaddi_du LSX 0111 00101000 10111 imm:5 vj:5 vd:5
+vsubi_bu LSX 0111 00101000 11000 imm:5 vj:5 vd:5
+vsubi_hu LSX 0111 00101000 11001 imm:5 vj:5 vd:5
+vsubi_wu LSX 0111 00101000 11010 imm:5 vj:5 vd:5
+vsubi_du LSX 0111 00101000 11011 imm:5 vj:5 vd:5
+
+vneg_b LSX 0111 00101001 11000 01100 vj:5 vd:5
+vneg_h LSX 0111 00101001 11000 01101 vj:5 vd:5
+vneg_w LSX 0111 00101001 11000 01110 vj:5 vd:5
+vneg_d LSX 0111 00101001 11000 01111 vj:5 vd:5
+
+vsadd_b LSX 0111 00000100 01100 vk:5 vj:5 vd:5
+vsadd_h LSX 0111 00000100 01101 vk:5 vj:5 vd:5
+vsadd_w LSX 0111 00000100 01110 vk:5 vj:5 vd:5
+vsadd_d LSX 0111 00000100 01111 vk:5 vj:5 vd:5
+vsadd_bu LSX 0111 00000100 10100 vk:5 vj:5 vd:5
+vsadd_hu LSX 0111 00000100 10101 vk:5 vj:5 vd:5
+vsadd_wu LSX 0111 00000100 10110 vk:5 vj:5 vd:5
+vsadd_du LSX 0111 00000100 10111 vk:5 vj:5 vd:5
+
+vssub_b LSX 0111 00000100 10000 vk:5 vj:5 vd:5
+vssub_h LSX 0111 00000100 10001 vk:5 vj:5 vd:5
+vssub_w LSX 0111 00000100 10010 vk:5 vj:5 vd:5
+vssub_d LSX 0111 00000100 10011 vk:5 vj:5 vd:5
+vssub_bu LSX 0111 00000100 11000 vk:5 vj:5 vd:5
+vssub_hu LSX 0111 00000100 11001 vk:5 vj:5 vd:5
+vssub_wu LSX 0111 00000100 11010 vk:5 vj:5 vd:5
+vssub_du LSX 0111 00000100 11011 vk:5 vj:5 vd:5
+
+vhaddw_h_b LSX 0111 00000101 01000 vk:5 vj:5 vd:5
+vhaddw_w_h LSX 0111 00000101 01001 vk:5 vj:5 vd:5
+vhaddw_d_w LSX 0111 00000101 01010 vk:5 vj:5 vd:5
+vhaddw_q_d LSX 0111 00000101 01011 vk:5 vj:5 vd:5
+vhaddw_hu_bu LSX 0111 00000101 10000 vk:5 vj:5 vd:5
+vhaddw_wu_hu LSX 0111 00000101 10001 vk:5 vj:5 vd:5
+vhaddw_du_wu LSX 0111 00000101 10010 vk:5 vj:5 vd:5
+vhaddw_qu_du LSX 0111 00000101 10011 vk:5 vj:5 vd:5
+
+vhsubw_h_b LSX 0111 00000101 01100 vk:5 vj:5 vd:5
+vhsubw_w_h LSX 0111 00000101 01101 vk:5 vj:5 vd:5
+vhsubw_d_w LSX 0111 00000101 01110 vk:5 vj:5 vd:5
+vhsubw_q_d LSX 0111 00000101 01111 vk:5 vj:5 vd:5
+vhsubw_hu_bu LSX 0111 00000101 10100 vk:5 vj:5 vd:5
+vhsubw_wu_hu LSX 0111 00000101 10101 vk:5 vj:5 vd:5
+vhsubw_du_wu LSX 0111 00000101 10110 vk:5 vj:5 vd:5
+vhsubw_qu_du LSX 0111 00000101 10111 vk:5 vj:5 vd:5
+
+vaddwev_h_b LSX 0111 00000001 11100 vk:5 vj:5 vd:5
+vaddwev_w_h LSX 0111 00000001 11101 vk:5 vj:5 vd:5
+vaddwev_d_w LSX 0111 00000001 11110 vk:5 vj:5 vd:5
+vaddwev_q_d LSX 0111 00000001 11111 vk:5 vj:5 vd:5
+vaddwod_h_b LSX 0111 00000010 00100 vk:5 vj:5 vd:5
+vaddwod_w_h LSX 0111 00000010 00101 vk:5 vj:5 vd:5
+vaddwod_d_w LSX 0111 00000010 00110 vk:5 vj:5 vd:5
+vaddwod_q_d LSX 0111 00000010 00111 vk:5 vj:5 vd:5
+
+vsubwev_h_b LSX 0111 00000010 00000 vk:5 vj:5 vd:5
+vsubwev_w_h LSX 0111 00000010 00001 vk:5 vj:5 vd:5
+vsubwev_d_w LSX 0111 00000010 00010 vk:5 vj:5 vd:5
+vsubwev_q_d LSX 0111 00000010 00011 vk:5 vj:5 vd:5
+vsubwod_h_b LSX 0111 00000010 01000 vk:5 vj:5 vd:5
+vsubwod_w_h LSX 0111 00000010 01001 vk:5 vj:5 vd:5
+vsubwod_d_w LSX 0111 00000010 01010 vk:5 vj:5 vd:5
+vsubwod_q_d LSX 0111 00000010 01011 vk:5 vj:5 vd:5
+
+vaddwev_h_bu LSX 0111 00000010 11100 vk:5 vj:5 vd:5
+vaddwev_w_hu LSX 0111 00000010 11101 vk:5 vj:5 vd:5
+vaddwev_d_wu LSX 0111 00000010 11110 vk:5 vj:5 vd:5
+vaddwev_q_du LSX 0111 00000010 11111 vk:5 vj:5 vd:5
+vaddwod_h_bu LSX 0111 00000011 00100 vk:5 vj:5 vd:5
+vaddwod_w_hu LSX 0111 00000011 00101 vk:5 vj:5 vd:5
+vaddwod_d_wu LSX 0111 00000011 00110 vk:5 vj:5 vd:5
+vaddwod_q_du LSX 0111 00000011 00111 vk:5 vj:5 vd:5
+
+vsubwev_h_bu LSX 0111 00000011 00000 vk:5 vj:5 vd:5
+vsubwev_w_hu LSX 0111 00000011 00001 vk:5 vj:5 vd:5
+vsubwev_d_wu LSX 0111 00000011 00010 vk:5 vj:5 vd:5
+vsubwev_q_du LSX 0111 00000011 00011 vk:5 vj:5 vd:5
+vsubwod_h_bu LSX 0111 00000011 01000 vk:5 vj:5 vd:5
+vsubwod_w_hu LSX 0111 00000011 01001 vk:5 vj:5 vd:5
+vsubwod_d_wu LSX 0111 00000011 01010 vk:5 vj:5 vd:5
+vsubwod_q_du LSX 0111 00000011 01011 vk:5 vj:5 vd:5
+
+vaddwev_h_bu_b LSX 0111 00000011 11100 vk:5 vj:5 vd:5
+vaddwev_w_hu_h LSX 0111 00000011 11101 vk:5 vj:5 vd:5
+vaddwev_d_wu_w LSX 0111 00000011 11110 vk:5 vj:5 vd:5
+vaddwev_q_du_d LSX 0111 00000011 11111 vk:5 vj:5 vd:5
+vaddwod_h_bu_b LSX 0111 00000100 00000 vk:5 vj:5 vd:5
+vaddwod_w_hu_h LSX 0111 00000100 00001 vk:5 vj:5 vd:5
+vaddwod_d_wu_w LSX 0111 00000100 00010 vk:5 vj:5 vd:5
+vaddwod_q_du_d LSX 0111 00000100 00011 vk:5 vj:5 vd:5
+
+vavg_b LSX 0111 00000110 01000 vk:5 vj:5 vd:5
+vavg_h LSX 0111 00000110 01001 vk:5 vj:5 vd:5
+vavg_w LSX 0111 00000110 01010 vk:5 vj:5 vd:5
+vavg_d LSX 0111 00000110 01011 vk:5 vj:5 vd:5
+vavg_bu LSX 0111 00000110 01100 vk:5 vj:5 vd:5
+vavg_hu LSX 0111 00000110 01101 vk:5 vj:5 vd:5
+vavg_wu LSX 0111 00000110 01110 vk:5 vj:5 vd:5
+vavg_du LSX 0111 00000110 01111 vk:5 vj:5 vd:5
+vavgr_b LSX 0111 00000110 10000 vk:5 vj:5 vd:5
+vavgr_h LSX 0111 00000110 10001 vk:5 vj:5 vd:5
+vavgr_w LSX 0111 00000110 10010 vk:5 vj:5 vd:5
+vavgr_d LSX 0111 00000110 10011 vk:5 vj:5 vd:5
+vavgr_bu LSX 0111 00000110 10100 vk:5 vj:5 vd:5
+vavgr_hu LSX 0111 00000110 10101 vk:5 vj:5 vd:5
+vavgr_wu LSX 0111 00000110 10110 vk:5 vj:5 vd:5
+vavgr_du LSX 0111 00000110 10111 vk:5 vj:5 vd:5
+
+vabsd_b LSX 0111 00000110 00000 vk:5 vj:5 vd:5
+vabsd_h LSX 0111 00000110 00001 vk:5 vj:5 vd:5
+vabsd_w LSX 0111 00000110 00010 vk:5 vj:5 vd:5
+vabsd_d LSX 0111 00000110 00011 vk:5 vj:5 vd:5
+vabsd_bu LSX 0111 00000110 00100 vk:5 vj:5 vd:5
+vabsd_hu LSX 0111 00000110 00101 vk:5 vj:5 vd:5
+vabsd_wu LSX 0111 00000110 00110 vk:5 vj:5 vd:5
+vabsd_du LSX 0111 00000110 00111 vk:5 vj:5 vd:5
+
+vadda_b LSX 0111 00000101 11000 vk:5 vj:5 vd:5
+vadda_h LSX 0111 00000101 11001 vk:5 vj:5 vd:5
+vadda_w LSX 0111 00000101 11010 vk:5 vj:5 vd:5
+vadda_d LSX 0111 00000101 11011 vk:5 vj:5 vd:5
+
+vmax_b LSX 0111 00000111 00000 vk:5 vj:5 vd:5
+vmax_h LSX 0111 00000111 00001 vk:5 vj:5 vd:5
+vmax_w LSX 0111 00000111 00010 vk:5 vj:5 vd:5
+vmax_d LSX 0111 00000111 00011 vk:5 vj:5 vd:5
+
+vmaxi_b LSX 0111 00101001 00000 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+vmaxi_h LSX 0111 00101001 00001 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+vmaxi_w LSX 0111 00101001 00010 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+vmaxi_d LSX 0111 00101001 00011 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+
+vmax_bu LSX 0111 00000111 01000 vk:5 vj:5 vd:5
+vmax_hu LSX 0111 00000111 01001 vk:5 vj:5 vd:5
+vmax_wu LSX 0111 00000111 01010 vk:5 vj:5 vd:5
+vmax_du LSX 0111 00000111 01011 vk:5 vj:5 vd:5
+vmaxi_bu LSX 0111 00101001 01000 imm:5 vj:5 vd:5
+vmaxi_hu LSX 0111 00101001 01001 imm:5 vj:5 vd:5
+vmaxi_wu LSX 0111 00101001 01010 imm:5 vj:5 vd:5
+vmaxi_du LSX 0111 00101001 01011 imm:5 vj:5 vd:5
+
+vmin_b LSX 0111 00000111 00100 vk:5 vj:5 vd:5
+vmin_h LSX 0111 00000111 00101 vk:5 vj:5 vd:5
+vmin_w LSX 0111 00000111 00110 vk:5 vj:5 vd:5
+vmin_d LSX 0111 00000111 00111 vk:5 vj:5 vd:5
+vmini_b LSX 0111 00101001 00100 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+vmini_h LSX 0111 00101001 00101 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+vmini_w LSX 0111 00101001 00110 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+vmini_d LSX 0111 00101001 00111 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+
+vmin_bu LSX 0111 00000111 01100 vk:5 vj:5 vd:5
+vmin_hu LSX 0111 00000111 01101 vk:5 vj:5 vd:5
+vmin_wu LSX 0111 00000111 01110 vk:5 vj:5 vd:5
+vmin_du LSX 0111 00000111 01111 vk:5 vj:5 vd:5
+vmini_bu LSX 0111 00101001 01100 imm:5 vj:5 vd:5
+vmini_hu LSX 0111 00101001 01101 imm:5 vj:5 vd:5
+vmini_wu LSX 0111 00101001 01110 imm:5 vj:5 vd:5
+vmini_du LSX 0111 00101001 01111 imm:5 vj:5 vd:5
+
+vmul_b LSX 0111 00001000 01000 vk:5 vj:5 vd:5
+vmul_h LSX 0111 00001000 01001 vk:5 vj:5 vd:5
+vmul_w LSX 0111 00001000 01010 vk:5 vj:5 vd:5
+vmul_d LSX 0111 00001000 01011 vk:5 vj:5 vd:5
+vmuh_b LSX 0111 00001000 01100 vk:5 vj:5 vd:5
+vmuh_h LSX 0111 00001000 01101 vk:5 vj:5 vd:5
+vmuh_w LSX 0111 00001000 01110 vk:5 vj:5 vd:5
+vmuh_d LSX 0111 00001000 01111 vk:5 vj:5 vd:5
+vmuh_bu LSX 0111 00001000 10000 vk:5 vj:5 vd:5
+vmuh_hu LSX 0111 00001000 10001 vk:5 vj:5 vd:5
+vmuh_wu LSX 0111 00001000 10010 vk:5 vj:5 vd:5
+vmuh_du LSX 0111 00001000 10011 vk:5 vj:5 vd:5
+
+vmulwev_h_b LSX 0111 00001001 00000 vk:5 vj:5 vd:5
+vmulwev_w_h LSX 0111 00001001 00001 vk:5 vj:5 vd:5
+vmulwev_d_w LSX 0111 00001001 00010 vk:5 vj:5 vd:5
+vmulwev_q_d LSX 0111 00001001 00011 vk:5 vj:5 vd:5
+vmulwod_h_b LSX 0111 00001001 00100 vk:5 vj:5 vd:5
+vmulwod_w_h LSX 0111 00001001 00101 vk:5 vj:5 vd:5
+vmulwod_d_w LSX 0111 00001001 00110 vk:5 vj:5 vd:5
+vmulwod_q_d LSX 0111 00001001 00111 vk:5 vj:5 vd:5
+vmulwev_h_bu LSX 0111 00001001 10000 vk:5 vj:5 vd:5
+vmulwev_w_hu LSX 0111 00001001 10001 vk:5 vj:5 vd:5
+vmulwev_d_wu LSX 0111 00001001 10010 vk:5 vj:5 vd:5
+vmulwev_q_du LSX 0111 00001001 10011 vk:5 vj:5 vd:5
+vmulwod_h_bu LSX 0111 00001001 10100 vk:5 vj:5 vd:5
+vmulwod_w_hu LSX 0111 00001001 10101 vk:5 vj:5 vd:5
+vmulwod_d_wu LSX 0111 00001001 10110 vk:5 vj:5 vd:5
+vmulwod_q_du LSX 0111 00001001 10111 vk:5 vj:5 vd:5
+vmulwev_h_bu_b LSX 0111 00001010 00000 vk:5 vj:5 vd:5
+vmulwev_w_hu_h LSX 0111 00001010 00001 vk:5 vj:5 vd:5
+vmulwev_d_wu_w LSX 0111 00001010 00010 vk:5 vj:5 vd:5
+vmulwev_q_du_d LSX 0111 00001010 00011 vk:5 vj:5 vd:5
+vmulwod_h_bu_b LSX 0111 00001010 00100 vk:5 vj:5 vd:5
+vmulwod_w_hu_h LSX 0111 00001010 00101 vk:5 vj:5 vd:5
+vmulwod_d_wu_w LSX 0111 00001010 00110 vk:5 vj:5 vd:5
+vmulwod_q_du_d LSX 0111 00001010 00111 vk:5 vj:5 vd:5
+
+vmadd_b LSX 0111 00001010 10000 vk:5 vj:5 vd:5
+vmadd_h LSX 0111 00001010 10001 vk:5 vj:5 vd:5
+vmadd_w LSX 0111 00001010 10010 vk:5 vj:5 vd:5
+vmadd_d LSX 0111 00001010 10011 vk:5 vj:5 vd:5
+vmsub_b LSX 0111 00001010 10100 vk:5 vj:5 vd:5
+vmsub_h LSX 0111 00001010 10101 vk:5 vj:5 vd:5
+vmsub_w LSX 0111 00001010 10110 vk:5 vj:5 vd:5
+vmsub_d LSX 0111 00001010 10111 vk:5 vj:5 vd:5
+
+vmaddwev_h_b LSX 0111 00001010 11000 vk:5 vj:5 vd:5
+vmaddwev_w_h LSX 0111 00001010 11001 vk:5 vj:5 vd:5
+vmaddwev_d_w LSX 0111 00001010 11010 vk:5 vj:5 vd:5
+vmaddwev_q_d LSX 0111 00001010 11011 vk:5 vj:5 vd:5
+vmaddwod_h_b LSX 0111 00001010 11100 vk:5 vj:5 vd:5
+vmaddwod_w_h LSX 0111 00001010 11101 vk:5 vj:5 vd:5
+vmaddwod_d_w LSX 0111 00001010 11110 vk:5 vj:5 vd:5
+vmaddwod_q_d LSX 0111 00001010 11111 vk:5 vj:5 vd:5
+vmaddwev_h_bu LSX 0111 00001011 01000 vk:5 vj:5 vd:5
+vmaddwev_w_hu LSX 0111 00001011 01001 vk:5 vj:5 vd:5
+vmaddwev_d_wu LSX 0111 00001011 01010 vk:5 vj:5 vd:5
+vmaddwev_q_du LSX 0111 00001011 01011 vk:5 vj:5 vd:5
+vmaddwod_h_bu LSX 0111 00001011 01100 vk:5 vj:5 vd:5
+vmaddwod_w_hu LSX 0111 00001011 01101 vk:5 vj:5 vd:5
+vmaddwod_d_wu LSX 0111 00001011 01110 vk:5 vj:5 vd:5
+vmaddwod_q_du LSX 0111 00001011 01111 vk:5 vj:5 vd:5
+vmaddwev_h_bu_b LSX 0111 00001011 11000 vk:5 vj:5 vd:5
+vmaddwev_w_hu_h LSX 0111 00001011 11001 vk:5 vj:5 vd:5
+vmaddwev_d_wu_w LSX 0111 00001011 11010 vk:5 vj:5 vd:5
+vmaddwev_q_du_d LSX 0111 00001011 11011 vk:5 vj:5 vd:5
+vmaddwod_h_bu_b LSX 0111 00001011 11100 vk:5 vj:5 vd:5
+vmaddwod_w_hu_h LSX 0111 00001011 11101 vk:5 vj:5 vd:5
+vmaddwod_d_wu_w LSX 0111 00001011 11110 vk:5 vj:5 vd:5
+vmaddwod_q_du_d LSX 0111 00001011 11111 vk:5 vj:5 vd:5
+
+vdiv_b LSX 0111 00001110 00000 vk:5 vj:5 vd:5
+vdiv_h LSX 0111 00001110 00001 vk:5 vj:5 vd:5
+vdiv_w LSX 0111 00001110 00010 vk:5 vj:5 vd:5
+vdiv_d LSX 0111 00001110 00011 vk:5 vj:5 vd:5
+vdiv_bu LSX 0111 00001110 01000 vk:5 vj:5 vd:5
+vdiv_hu LSX 0111 00001110 01001 vk:5 vj:5 vd:5
+vdiv_wu LSX 0111 00001110 01010 vk:5 vj:5 vd:5
+vdiv_du LSX 0111 00001110 01011 vk:5 vj:5 vd:5
+vmod_b LSX 0111 00001110 00100 vk:5 vj:5 vd:5
+vmod_h LSX 0111 00001110 00101 vk:5 vj:5 vd:5
+vmod_w LSX 0111 00001110 00110 vk:5 vj:5 vd:5
+vmod_d LSX 0111 00001110 00111 vk:5 vj:5 vd:5
+vmod_bu LSX 0111 00001110 01100 vk:5 vj:5 vd:5
+vmod_hu LSX 0111 00001110 01101 vk:5 vj:5 vd:5
+vmod_wu LSX 0111 00001110 01110 vk:5 vj:5 vd:5
+vmod_du LSX 0111 00001110 01111 vk:5 vj:5 vd:5
+
+vsat_b LSX 0111 00110010 01000 01 imm:3 vj:5 vd:5
+vsat_h LSX 0111 00110010 01000 1 imm:4 vj:5 vd:5
+vsat_w LSX 0111 00110010 01001 imm:5 vj:5 vd:5
+vsat_d LSX 0111 00110010 0101 imm:6 vj:5 vd:5
+vsat_bu LSX 0111 00110010 10000 01 imm:3 vj:5 vd:5
+vsat_hu LSX 0111 00110010 10000 1 imm:4 vj:5 vd:5
+vsat_wu LSX 0111 00110010 10001 imm:5 vj:5 vd:5
+vsat_du LSX 0111 00110010 1001 imm:6 vj:5 vd:5
+
+vexth_h_b LSX 0111 00101001 11101 11000 vj:5 vd:5
+vexth_w_h LSX 0111 00101001 11101 11001 vj:5 vd:5
+vexth_d_w LSX 0111 00101001 11101 11010 vj:5 vd:5
+vexth_q_d LSX 0111 00101001 11101 11011 vj:5 vd:5
+vexth_hu_bu LSX 0111 00101001 11101 11100 vj:5 vd:5
+vexth_wu_hu LSX 0111 00101001 11101 11101 vj:5 vd:5
+vexth_du_wu LSX 0111 00101001 11101 11110 vj:5 vd:5
+vexth_qu_du LSX 0111 00101001 11101 11111 vj:5 vd:5
+
+vsigncov_b LSX 0111 00010010 11100 vk:5 vj:5 vd:5
+vsigncov_h LSX 0111 00010010 11101 vk:5 vj:5 vd:5
+vsigncov_w LSX 0111 00010010 11110 vk:5 vj:5 vd:5
+vsigncov_d LSX 0111 00010010 11111 vk:5 vj:5 vd:5
+
+vmskltz_b LSX 0111 00101001 11000 10000 vj:5 vd:5
+vmskltz_h LSX 0111 00101001 11000 10001 vj:5 vd:5
+vmskltz_w LSX 0111 00101001 11000 10010 vj:5 vd:5
+vmskltz_d LSX 0111 00101001 11000 10011 vj:5 vd:5
+vmskgez_b LSX 0111 00101001 11000 10100 vj:5 vd:5
+vmsknz_b LSX 0111 00101001 11000 11000 vj:5 vd:5
+
+vand_v LSX 0111 00010010 01100 vk:5 vj:5 vd:5
+vor_v LSX 0111 00010010 01101 vk:5 vj:5 vd:5
+vxor_v LSX 0111 00010010 01110 vk:5 vj:5 vd:5
+vnor_v LSX 0111 00010010 01111 vk:5 vj:5 vd:5
+vandn_v LSX 0111 00010010 10000 vk:5 vj:5 vd:5
+vorn_v LSX 0111 00010010 10001 vk:5 vj:5 vd:5
+
+vandi_b LSX 0111 00111101 00 imm:8 vj:5 vd:5
+vori_b LSX 0111 00111101 01 imm:8 vj:5 vd:5
+vxori_b LSX 0111 00111101 10 imm:8 vj:5 vd:5
+vnori_b LSX 0111 00111101 11 imm:8 vj:5 vd:5
+
+vsll_b LSX 0111 00001110 10000 vk:5 vj:5 vd:5
+vsll_h LSX 0111 00001110 10001 vk:5 vj:5 vd:5
+vsll_w LSX 0111 00001110 10010 vk:5 vj:5 vd:5
+vsll_d LSX 0111 00001110 10011 vk:5 vj:5 vd:5
+vslli_b LSX 0111 00110010 11000 01 imm:3 vj:5 vd:5
+vslli_h LSX 0111 00110010 11000 1 imm:4 vj:5 vd:5
+vslli_w LSX 0111 00110010 11001 imm:5 vj:5 vd:5
+vslli_d LSX 0111 00110010 1101 imm:6 vj:5 vd:5
+
+vsrl_b LSX 0111 00001110 10100 vk:5 vj:5 vd:5
+vsrl_h LSX 0111 00001110 10101 vk:5 vj:5 vd:5
+vsrl_w LSX 0111 00001110 10110 vk:5 vj:5 vd:5
+vsrl_d LSX 0111 00001110 10111 vk:5 vj:5 vd:5
+vsrli_b LSX 0111 00110011 00000 01 imm:3 vj:5 vd:5
+vsrli_h LSX 0111 00110011 00000 1 imm:4 vj:5 vd:5
+vsrli_w LSX 0111 00110011 00001 imm:5 vj:5 vd:5
+vsrli_d LSX 0111 00110011 0001 imm:6 vj:5 vd:5
+
+vsra_b LSX 0111 00001110 11000 vk:5 vj:5 vd:5
+vsra_h LSX 0111 00001110 11001 vk:5 vj:5 vd:5
+vsra_w LSX 0111 00001110 11010 vk:5 vj:5 vd:5
+vsra_d LSX 0111 00001110 11011 vk:5 vj:5 vd:5
+vsrai_b LSX 0111 00110011 01000 01 imm:3 vj:5 vd:5
+vsrai_h LSX 0111 00110011 01000 1 imm:4 vj:5 vd:5
+vsrai_w LSX 0111 00110011 01001 imm:5 vj:5 vd:5
+vsrai_d LSX 0111 00110011 0101 imm:6 vj:5 vd:5
+
+vrotr_b LSX 0111 00001110 11100 vk:5 vj:5 vd:5
+vrotr_h LSX 0111 00001110 11101 vk:5 vj:5 vd:5
+vrotr_w LSX 0111 00001110 11110 vk:5 vj:5 vd:5
+vrotr_d LSX 0111 00001110 11111 vk:5 vj:5 vd:5
+vrotri_b LSX 0111 00101010 00000 01 imm:3 vj:5 vd:5
+vrotri_h LSX 0111 00101010 00000 1 imm:4 vj:5 vd:5
+vrotri_w LSX 0111 00101010 00001 imm:5 vj:5 vd:5
+vrotri_d LSX 0111 00101010 0001 imm:6 vj:5 vd:5
+
+vsllwil_h_b LSX 0111 00110000 10000 01 imm:3 vj:5 vd:5
+vsllwil_w_h LSX 0111 00110000 10000 1 imm:4 vj:5 vd:5
+vsllwil_d_w LSX 0111 00110000 10001 imm:5 vj:5 vd:5
+vextl_q_d LSX 0111 00110000 10010 00000 vj:5 vd:5
+vsllwil_hu_bu LSX 0111 00110000 11000 01 imm:3 vj:5 vd:5
+vsllwil_wu_hu LSX 0111 00110000 11000 1 imm:4 vj:5 vd:5
+vsllwil_du_wu LSX 0111 00110000 11001 imm:5 vj:5 vd:5
+vextl_qu_du LSX 0111 00110000 11010 00000 vj:5 vd:5
+
+vsrlr_b LSX 0111 00001111 00000 vk:5 vj:5 vd:5
+vsrlr_h LSX 0111 00001111 00001 vk:5 vj:5 vd:5
+vsrlr_w LSX 0111 00001111 00010 vk:5 vj:5 vd:5
+vsrlr_d LSX 0111 00001111 00011 vk:5 vj:5 vd:5
+vsrlri_b LSX 0111 00101010 01000 01 imm:3 vj:5 vd:5
+vsrlri_h LSX 0111 00101010 01000 1 imm:4 vj:5 vd:5
+vsrlri_w LSX 0111 00101010 01001 imm:5 vj:5 vd:5
+vsrlri_d LSX 0111 00101010 0101 imm:6 vj:5 vd:5
+
+vsrar_b LSX 0111 00001111 00100 vk:5 vj:5 vd:5
+vsrar_h LSX 0111 00001111 00101 vk:5 vj:5 vd:5
+vsrar_w LSX 0111 00001111 00110 vk:5 vj:5 vd:5
+vsrar_d LSX 0111 00001111 00111 vk:5 vj:5 vd:5
+vsrari_b LSX 0111 00101010 10000 01 imm:3 vj:5 vd:5
+vsrari_h LSX 0111 00101010 10000 1 imm:4 vj:5 vd:5
+vsrari_w LSX 0111 00101010 10001 imm:5 vj:5 vd:5
+vsrari_d LSX 0111 00101010 1001 imm:6 vj:5 vd:5
+
+vsrln_b_h LSX 0111 00001111 01001 vk:5 vj:5 vd:5
+vsrln_h_w LSX 0111 00001111 01010 vk:5 vj:5 vd:5
+vsrln_w_d LSX 0111 00001111 01011 vk:5 vj:5 vd:5
+vsran_b_h LSX 0111 00001111 01101 vk:5 vj:5 vd:5
+vsran_h_w LSX 0111 00001111 01110 vk:5 vj:5 vd:5
+vsran_w_d LSX 0111 00001111 01111 vk:5 vj:5 vd:5
+
+vsrlni_b_h LSX 0111 00110100 00000 1 imm:4 vj:5 vd:5
+vsrlni_h_w LSX 0111 00110100 00001 imm:5 vj:5 vd:5
+vsrlni_w_d LSX 0111 00110100 0001 imm:6 vj:5 vd:5
+vsrlni_d_q LSX 0111 00110100 001 imm:7 vj:5 vd:5
+vsrani_b_h LSX 0111 00110101 10000 1 imm:4 vj:5 vd:5
+vsrani_h_w LSX 0111 00110101 10001 imm:5 vj:5 vd:5
+vsrani_w_d LSX 0111 00110101 1001 imm:6 vj:5 vd:5
+vsrani_d_q LSX 0111 00110101 101 imm:7 vj:5 vd:5
+
+vsrlrn_b_h LSX 0111 00001111 10001 vk:5 vj:5 vd:5
+vsrlrn_h_w LSX 0111 00001111 10010 vk:5 vj:5 vd:5
+vsrlrn_w_d LSX 0111 00001111 10011 vk:5 vj:5 vd:5
+vsrarn_b_h LSX 0111 00001111 10101 vk:5 vj:5 vd:5
+vsrarn_h_w LSX 0111 00001111 10110 vk:5 vj:5 vd:5
+vsrarn_w_d LSX 0111 00001111 10111 vk:5 vj:5 vd:5
+
+vsrlrni_b_h LSX 0111 00110100 01000 1 imm:4 vj:5 vd:5
+vsrlrni_h_w LSX 0111 00110100 01001 imm:5 vj:5 vd:5
+vsrlrni_w_d LSX 0111 00110100 0101 imm:6 vj:5 vd:5
+vsrlrni_d_q LSX 0111 00110100 011 imm:7 vj:5 vd:5
+vsrarni_b_h LSX 0111 00110101 11000 1 imm:4 vj:5 vd:5
+vsrarni_h_w LSX 0111 00110101 11001 imm:5 vj:5 vd:5
+vsrarni_w_d LSX 0111 00110101 1101 imm:6 vj:5 vd:5
+vsrarni_d_q LSX 0111 00110101 111 imm:7 vj:5 vd:5
+
+vssrln_b_h LSX 0111 00001111 11001 vk:5 vj:5 vd:5
+vssrln_h_w LSX 0111 00001111 11010 vk:5 vj:5 vd:5
+vssrln_w_d LSX 0111 00001111 11011 vk:5 vj:5 vd:5
+vssran_b_h LSX 0111 00001111 11101 vk:5 vj:5 vd:5
+vssran_h_w LSX 0111 00001111 11110 vk:5 vj:5 vd:5
+vssran_w_d LSX 0111 00001111 11111 vk:5 vj:5 vd:5
+vssrln_bu_h LSX 0111 00010000 01001 vk:5 vj:5 vd:5
+vssrln_hu_w LSX 0111 00010000 01010 vk:5 vj:5 vd:5
+vssrln_wu_d LSX 0111 00010000 01011 vk:5 vj:5 vd:5
+vssran_bu_h LSX 0111 00010000 01101 vk:5 vj:5 vd:5
+vssran_hu_w LSX 0111 00010000 01110 vk:5 vj:5 vd:5
+vssran_wu_d LSX 0111 00010000 01111 vk:5 vj:5 vd:5
+
+vssrlni_b_h LSX 0111 00110100 10000 1 imm:4 vj:5 vd:5
+vssrlni_h_w LSX 0111 00110100 10001 imm:5 vj:5 vd:5
+vssrlni_w_d LSX 0111 00110100 1001 imm:6 vj:5 vd:5
+vssrlni_d_q LSX 0111 00110100 101 imm:7 vj:5 vd:5
+vssrani_b_h LSX 0111 00110110 00000 1 imm:4 vj:5 vd:5
+vssrani_h_w LSX 0111 00110110 00001 imm:5 vj:5 vd:5
+vssrani_w_d LSX 0111 00110110 0001 imm:6 vj:5 vd:5
+vssrani_d_q LSX 0111 00110110 001 imm:7 vj:5 vd:5
+vssrlni_bu_h LSX 0111 00110100 11000 1 imm:4 vj:5 vd:5
+vssrlni_hu_w LSX 0111 00110100 11001 imm:5 vj:5 vd:5
+vssrlni_wu_d LSX 0111 00110100 1101 imm:6 vj:5 vd:5
+vssrlni_du_q LSX 0111 00110100 111 imm:7 vj:5 vd:5
+vssrani_bu_h LSX 0111 00110110 01000 1 imm:4 vj:5 vd:5
+vssrani_hu_w LSX 0111 00110110 01001 imm:5 vj:5 vd:5
+vssrani_wu_d LSX 0111 00110110 0101 imm:6 vj:5 vd:5
+vssrani_du_q LSX 0111 00110110 011 imm:7 vj:5 vd:5
+
+vssrlrn_b_h LSX 0111 00010000 00001 vk:5 vj:5 vd:5
+vssrlrn_h_w LSX 0111 00010000 00010 vk:5 vj:5 vd:5
+vssrlrn_w_d LSX 0111 00010000 00011 vk:5 vj:5 vd:5
+vssrarn_b_h LSX 0111 00010000 00101 vk:5 vj:5 vd:5
+vssrarn_h_w LSX 0111 00010000 00110 vk:5 vj:5 vd:5
+vssrarn_w_d LSX 0111 00010000 00111 vk:5 vj:5 vd:5
+vssrlrn_bu_h LSX 0111 00010000 10001 vk:5 vj:5 vd:5
+vssrlrn_hu_w LSX 0111 00010000 10010 vk:5 vj:5 vd:5
+vssrlrn_wu_d LSX 0111 00010000 10011 vk:5 vj:5 vd:5
+vssrarn_bu_h LSX 0111 00010000 10101 vk:5 vj:5 vd:5
+vssrarn_hu_w LSX 0111 00010000 10110 vk:5 vj:5 vd:5
+vssrarn_wu_d LSX 0111 00010000 10111 vk:5 vj:5 vd:5
+
+vssrlrni_b_h LSX 0111 00110101 00000 1 imm:4 vj:5 vd:5
+vssrlrni_h_w LSX 0111 00110101 00001 imm:5 vj:5 vd:5
+vssrlrni_w_d LSX 0111 00110101 0001 imm:6 vj:5 vd:5
+vssrlrni_d_q LSX 0111 00110101 001 imm:7 vj:5 vd:5
+vssrarni_b_h LSX 0111 00110110 10000 1 imm:4 vj:5 vd:5
+vssrarni_h_w LSX 0111 00110110 10001 imm:5 vj:5 vd:5
+vssrarni_w_d LSX 0111 00110110 1001 imm:6 vj:5 vd:5
+vssrarni_d_q LSX 0111 00110110 101 imm:7 vj:5 vd:5
+vssrlrni_hu_w LSX 0111 00110101 01001 imm:5 vj:5 vd:5
+vssrlrni_wu_d LSX 0111 00110101 0101 imm:6 vj:5 vd:5
+vssrlrni_du_q LSX 0111 00110101 011 imm:7 vj:5 vd:5
+vssrarni_bu_h LSX 0111 00110110 11000 1 imm:4 vj:5 vd:5
+vssrarni_hu_w LSX 0111 00110110 11001 imm:5 vj:5 vd:5
+vssrarni_wu_d LSX 0111 00110110 1101 imm:6 vj:5 vd:5
+vssrarni_du_q LSX 0111 00110110 111 imm:7 vj:5 vd:5
+
+vclo_b LSX 0111 00101001 11000 00000 vj:5 vd:5
+vclo_h LSX 0111 00101001 11000 00001 vj:5 vd:5
+vclo_w LSX 0111 00101001 11000 00010 vj:5 vd:5
+vclo_d LSX 0111 00101001 11000 00011 vj:5 vd:5
+vclz_b LSX 0111 00101001 11000 00100 vj:5 vd:5
+vclz_h LSX 0111 00101001 11000 00101 vj:5 vd:5
+vclz_w LSX 0111 00101001 11000 00110 vj:5 vd:5
+vclz_d LSX 0111 00101001 11000 00111 vj:5 vd:5
+
+vpcnt_b LSX 0111 00101001 11000 01000 vj:5 vd:5
+vpcnt_h LSX 0111 00101001 11000 01001 vj:5 vd:5
+vpcnt_w LSX 0111 00101001 11000 01010 vj:5 vd:5
+vpcnt_d LSX 0111 00101001 11000 01011 vj:5 vd:5
+
+vbitclr_b LSX 0111 00010000 11000 vk:5 vj:5 vd:5
+vbitclr_h LSX 0111 00010000 11001 vk:5 vj:5 vd:5
+vbitclr_w LSX 0111 00010000 11010 vk:5 vj:5 vd:5
+vbitclr_d LSX 0111 00010000 11011 vk:5 vj:5 vd:5
+vbitclri_b LSX 0111 00110001 00000 01 imm:3 vj:5 vd:5
+vbitclri_h LSX 0111 00110001 00000 1 imm:4 vj:5 vd:5
+vbitclri_w LSX 0111 00110001 00001 imm:5 vj:5 vd:5
+vbitclri_d LSX 0111 00110001 0001 imm:6 vj:5 vd:5
+vbitset_b LSX 0111 00010000 11100 vk:5 vj:5 vd:5
+vbitset_h LSX 0111 00010000 11101 vk:5 vj:5 vd:5
+vbitset_w LSX 0111 00010000 11110 vk:5 vj:5 vd:5
+vbitset_d LSX 0111 00010000 11111 vk:5 vj:5 vd:5
+vbitseti_b LSX 0111 00110001 01000 01 imm:3 vj:5 vd:5
+vbitseti_h LSX 0111 00110001 01000 1 imm:4 vj:5 vd:5
+vbitseti_w LSX 0111 00110001 01001 imm:5 vj:5 vd:5
+vbitseti_d LSX 0111 00110001 0101 imm:6 vj:5 vd:5
+vbitrev_b LSX 0111 00010001 00000 vk:5 vj:5 vd:5
+vbitrev_h LSX 0111 00010001 00001 vk:5 vj:5 vd:5
+vbitrev_w LSX 0111 00010001 00010 vk:5 vj:5 vd:5
+vbitrev_d LSX 0111 00010001 00011 vk:5 vj:5 vd:5
+vbitrevi_b LSX 0111 00110001 10000 01 imm:3 vj:5 vd:5
+vbitrevi_h LSX 0111 00110001 10000 1 imm:4 vj:5 vd:5
+vbitrevi_w LSX 0111 00110001 10001 imm:5 vj:5 vd:5
+vbitrevi_d LSX 0111 00110001 1001 imm:6 vj:5 vd:5
+
+vfrstp_b LSX 0111 00010010 10110 vk:5 vj:5 vd:5
+vfrstp_h LSX 0111 00010010 10111 vk:5 vj:5 vd:5
+vfrstpi_b LSX 0111 00101001 10100 imm:5 vj:5 vd:5
+vfrstpi_h LSX 0111 00101001 10101 imm:5 vj:5 vd:5
+
+vfadd_s LSX 0111 00010011 00001 vk:5 vj:5 vd:5
+vfadd_d LSX 0111 00010011 00010 vk:5 vj:5 vd:5
+vfsub_s LSX 0111 00010011 00101 vk:5 vj:5 vd:5
+vfsub_d LSX 0111 00010011 00110 vk:5 vj:5 vd:5
+vfmul_s LSX 0111 00010011 10001 vk:5 vj:5 vd:5
+vfmul_d LSX 0111 00010011 10010 vk:5 vj:5 vd:5
+vfdiv_s LSX 0111 00010011 10101 vk:5 vj:5 vd:5
+vfdiv_d LSX 0111 00010011 10110 vk:5 vj:5 vd:5
+
+vfmadd_s LSX 0000 10010001 va:5 vk:5 vj:5 vd:5
+vfmadd_d LSX 0000 10010010 va:5 vk:5 vj:5 vd:5
+vfmsub_s LSX 0000 10010101 va:5 vk:5 vj:5 vd:5
+vfmsub_d LSX 0000 10010110 va:5 vk:5 vj:5 vd:5
+vfnmadd_s LSX 0000 10011001 va:5 vk:5 vj:5 vd:5
+vfnmadd_d LSX 0000 10011010 va:5 vk:5 vj:5 vd:5
+vfnmsub_s LSX 0000 10011101 va:5 vk:5 vj:5 vd:5
+vfnmsub_d LSX 0000 10011110 va:5 vk:5 vj:5 vd:5
+
+vfmax_s LSX 0111 00010011 11001 vk:5 vj:5 vd:5
+vfmax_d LSX 0111 00010011 11010 vk:5 vj:5 vd:5
+vfmin_s LSX 0111 00010011 11101 vk:5 vj:5 vd:5
+vfmin_d LSX 0111 00010011 11110 vk:5 vj:5 vd:5
+
+vfmaxa_s LSX 0111 00010100 00001 vk:5 vj:5 vd:5
+vfmaxa_d LSX 0111 00010100 00010 vk:5 vj:5 vd:5
+vfmina_s LSX 0111 00010100 00101 vk:5 vj:5 vd:5
+vfmina_d LSX 0111 00010100 00110 vk:5 vj:5 vd:5
+
+vflogb_s LSX 0111 00101001 11001 10001 vj:5 vd:5
+vflogb_d LSX 0111 00101001 11001 10010 vj:5 vd:5
+
+vfclass_s LSX 0111 00101001 11001 10101 vj:5 vd:5
+vfclass_d LSX 0111 00101001 11001 10110 vj:5 vd:5
+
+vfsqrt_s LSX 0111 00101001 11001 11001 vj:5 vd:5
+vfsqrt_d LSX 0111 00101001 11001 11010 vj:5 vd:5
+vfrecip_s LSX 0111 00101001 11001 11101 vj:5 vd:5
+vfrecip_d LSX 0111 00101001 11001 11110 vj:5 vd:5
+vfrsqrt_s LSX 0111 00101001 11010 00001 vj:5 vd:5
+vfrsqrt_d LSX 0111 00101001 11010 00010 vj:5 vd:5
+
+vfcvtl_s_h LSX 0111 00101001 11011 11010 vj:5 vd:5
+vfcvth_s_h LSX 0111 00101001 11011 11011 vj:5 vd:5
+vfcvtl_d_s LSX 0111 00101001 11011 11100 vj:5 vd:5
+vfcvth_d_s LSX 0111 00101001 11011 11101 vj:5 vd:5
+vfcvt_h_s LSX 0111 00010100 01100 vk:5 vj:5 vd:5
+vfcvt_s_d LSX 0111 00010100 01101 vk:5 vj:5 vd:5
+
+vfrint_s LSX 0111 00101001 11010 01101 vj:5 vd:5
+vfrint_d LSX 0111 00101001 11010 01110 vj:5 vd:5
+vfrintrm_s LSX 0111 00101001 11010 10001 vj:5 vd:5
+vfrintrm_d LSX 0111 00101001 11010 10010 vj:5 vd:5
+vfrintrp_s LSX 0111 00101001 11010 10101 vj:5 vd:5
+vfrintrp_d LSX 0111 00101001 11010 10110 vj:5 vd:5
+vfrintrz_s LSX 0111 00101001 11010 11001 vj:5 vd:5
+vfrintrz_d LSX 0111 00101001 11010 11010 vj:5 vd:5
+vfrintrne_s LSX 0111 00101001 11010 11101 vj:5 vd:5
+vfrintrne_d LSX 0111 00101001 11010 11110 vj:5 vd:5
+
+vftint_w_s LSX 0111 00101001 11100 01100 vj:5 vd:5
+vftint_l_d LSX 0111 00101001 11100 01101 vj:5 vd:5
+vftintrm_w_s LSX 0111 00101001 11100 01110 vj:5 vd:5
+vftintrm_l_d LSX 0111 00101001 11100 01111 vj:5 vd:5
+vftintrp_w_s LSX 0111 00101001 11100 10000 vj:5 vd:5
+vftintrp_l_d LSX 0111 00101001 11100 10001 vj:5 vd:5
+vftintrz_w_s LSX 0111 00101001 11100 10010 vj:5 vd:5
+vftintrz_l_d LSX 0111 00101001 11100 10011 vj:5 vd:5
+vftintrne_w_s LSX 0111 00101001 11100 10100 vj:5 vd:5
+vftintrne_l_d LSX 0111 00101001 11100 10101 vj:5 vd:5
+vftint_wu_s LSX 0111 00101001 11100 10110 vj:5 vd:5
+vftint_lu_d LSX 0111 00101001 11100 10111 vj:5 vd:5
+vftintrz_wu_s LSX 0111 00101001 11100 11100 vj:5 vd:5
+vftintrz_lu_d LSX 0111 00101001 11100 11101 vj:5 vd:5
+vftint_w_d LSX 0111 00010100 10011 vk:5 vj:5 vd:5
+vftintrm_w_d LSX 0111 00010100 10100 vk:5 vj:5 vd:5
+vftintrp_w_d LSX 0111 00010100 10101 vk:5 vj:5 vd:5
+vftintrz_w_d LSX 0111 00010100 10110 vk:5 vj:5 vd:5
+vftintrne_w_d LSX 0111 00010100 10111 vk:5 vj:5 vd:5
+vftintl_l_s LSX 0111 00101001 11101 00000 vj:5 vd:5
+vftinth_l_s LSX 0111 00101001 11101 00001 vj:5 vd:5
+vftintrml_l_s LSX 0111 00101001 11101 00010 vj:5 vd:5
+vftintrmh_l_s LSX 0111 00101001 11101 00011 vj:5 vd:5
+vftintrpl_l_s LSX 0111 00101001 11101 00100 vj:5 vd:5
+vftintrph_l_s LSX 0111 00101001 11101 00101 vj:5 vd:5
+vftintrzl_l_s LSX 0111 00101001 11101 00110 vj:5 vd:5
+vftintrzh_l_s LSX 0111 00101001 11101 00111 vj:5 vd:5
+vftintrnel_l_s LSX 0111 00101001 11101 01000 vj:5 vd:5
+vftintrneh_l_s LSX 0111 00101001 11101 01001 vj:5 vd:5
+
+vffint_s_w LSX 0111 00101001 11100 00000 vj:5 vd:5
+vffint_s_wu LSX 0111 00101001 11100 00001 vj:5 vd:5
+vffint_d_l LSX 0111 00101001 11100 00010 vj:5 vd:5
+vffint_d_lu LSX 0111 00101001 11100 00011 vj:5 vd:5
+vffintl_d_w LSX 0111 00101001 11100 00100 vj:5 vd:5
+vffinth_d_w LSX 0111 00101001 11100 00101 vj:5 vd:5
+vffint_s_l LSX 0111 00010100 10000 vk:5 vj:5 vd:5
+
+vseq_b LSX 0111 00000000 00000 vk:5 vj:5 vd:5
+vseq_h LSX 0111 00000000 00001 vk:5 vj:5 vd:5
+vseq_w LSX 0111 00000000 00010 vk:5 vj:5 vd:5
+vseq_d LSX 0111 00000000 00011 vk:5 vj:5 vd:5
+vseqi_b LSX 0111 00101000 00000 imm:5 vj:5 vd:5
+vseqi_h LSX 0111 00101000 00001 imm:5 vj:5 vd:5
+vseqi_w LSX 0111 00101000 00010 imm:5 vj:5 vd:5
+vseqi_d LSX 0111 00101000 00011 imm:5 vj:5 vd:5
+
+vsle_b LSX 0111 00000000 00100 vk:5 vj:5 vd:5
+vsle_h LSX 0111 00000000 00101 vk:5 vj:5 vd:5
+vsle_w LSX 0111 00000000 00110 vk:5 vj:5 vd:5
+vsle_d LSX 0111 00000000 00111 vk:5 vj:5 vd:5
+vslei_b LSX 0111 00101000 00100 imm:5 vj:5 vd:5
+vslei_h LSX 0111 00101000 00101 imm:5 vj:5 vd:5
+vslei_w LSX 0111 00101000 00110 imm:5 vj:5 vd:5
+vslei_d LSX 0111 00101000 00111 imm:5 vj:5 vd:5
+vsle_bu LSX 0111 00000000 01000 vk:5 vj:5 vd:5
+vsle_hu LSX 0111 00000000 01001 vk:5 vj:5 vd:5
+vsle_wu LSX 0111 00000000 01010 vk:5 vj:5 vd:5
+vsle_du LSX 0111 00000000 01011 vk:5 vj:5 vd:5
+vslei_bu LSX 0111 00101000 01000 imm:5 vj:5 vd:5
+vslei_hu LSX 0111 00101000 01000 imm:5 vj:5 vd:5
+vslei_wu LSX 0111 00101000 01010 imm:5 vj:5 vd:5
+vslei_du LSX 0111 00101000 01010 imm:5 vj:5 vd:5
+
+vslt_b LSX 0111 00000000 01100 vk:5 vj:5 vd:5
+vslt_h LSX 0111 00000000 01101 vk:5 vj:5 vd:5
+vslt_w LSX 0111 00000000 01110 vk:5 vj:5 vd:5
+vslt_d LSX 0111 00000000 01111 vk:5 vj:5 vd:5
+vslti_b LSX 0111 00101000 01100 imm:5 vj:5 vd:5
+vslti_h LSX 0111 00101000 01101 imm:5 vj:5 vd:5
+vslti_w LSX 0111 00101000 01110 imm:5 vj:5 vd:5
+vslti_d LSX 0111 00101000 01111 imm:5 vj:5 vd:5
+vslt_bu LSX 0111 00000000 10000 vk:5 vj:5 vd:5
+vslt_hu LSX 0111 00000000 10001 vk:5 vj:5 vd:5
+vslt_wu LSX 0111 00000000 10010 vk:5 vj:5 vd:5
+vslt_du LSX 0111 00000000 10011 vk:5 vj:5 vd:5
+vslti_bu LSX 0111 00101000 10000 imm:5 vj:5 vd:5
+vslti_hu LSX 0111 00101000 10001 imm:5 vj:5 vd:5
+vslti_wu LSX 0111 00101000 10010 imm:5 vj:5 vd:5
+vslti_du LSX 0111 00101000 10011 imm:5 vj:5 vd:5
+
+vfcmp_cond_s LSX 0000 11000101 cond:5 vk:5 vj:5 vd:5 \
+ !constraints { $cond > 0 && $cond < 0x12; }
+vfcmp_cond_d LSX 0000 11000110 cond:5 vk:5 vj:5 vd:5 \
+ !constraints { $cond > 0 && $cond < 0x12; }
+
+vbitsel_v LSX 0000 11010001 va:5 vk:5 vj:5 vd:5
+
+vbitseli_b LSX 0111 00111100 01 imm:8 vj:5 vd:5
+
+vseteqz_v LSX 0111 00101001 11001 00110 vj:5 00 cd:3
+vsetnez_v LSX 0111 00101001 11001 00111 vj:5 00 cd:3
+vsetanyeqz_b LSX 0111 00101001 11001 01000 vj:5 00 cd:3
+vsetanyeqz_h LSX 0111 00101001 11001 01001 vj:5 00 cd:3
+vsetanyeqz_w LSX 0111 00101001 11001 01010 vj:5 00 cd:3
+vsetanyeqz_d LSX 0111 00101001 11001 01011 vj:5 00 cd:3
+vsetallnez_b LSX 0111 00101001 11001 01100 vj:5 00 cd:3
+vsetallnez_h LSX 0111 00101001 11001 01101 vj:5 00 cd:3
+vsetallnez_w LSX 0111 00101001 11001 01110 vj:5 00 cd:3
+vsetallnez_d LSX 0111 00101001 11001 01111 vj:5 00 cd:3
+
+vinsgr2vr_b LSX 0111 00101110 10111 0 imm:4 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+vinsgr2vr_h LSX 0111 00101110 10111 10 imm:3 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+vinsgr2vr_w LSX 0111 00101110 10111 110 imm:2 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+vinsgr2vr_d LSX 0111 00101110 10111 1110 imm:1 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+vpickve2gr_b LSX 0111 00101110 11111 0 imm:4 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+vpickve2gr_h LSX 0111 00101110 11111 10 imm:3 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+vpickve2gr_w LSX 0111 00101110 11111 110 imm:2 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+vpickve2gr_d LSX 0111 00101110 11111 1110 imm:1 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+vpickve2gr_bu LSX 0111 00101111 00111 0 imm:4 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+vpickve2gr_hu LSX 0111 00101111 00111 10 imm:3 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+vpickve2gr_wu LSX 0111 00101111 00111 110 imm:2 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+vpickve2gr_du LSX 0111 00101111 00111 1110 imm:1 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+
+vreplgr2vr_b LSX 0111 00101001 11110 00000 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+vreplgr2vr_h LSX 0111 00101001 11110 00001 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+vreplgr2vr_w LSX 0111 00101001 11110 00010 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+vreplgr2vr_d LSX 0111 00101001 11110 00011 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+
+vreplve_b LSX 0111 00010010 00100 rk:5 vj:5 vd:5 \
+ !constraints { $rk != 2 && $rk != 0; }
+vreplve_h LSX 0111 00010010 00101 rk:5 vj:5 vd:5 \
+ !constraints { $rk != 2 && $rk != 0; }
+vreplve_w LSX 0111 00010010 00110 rk:5 vj:5 vd:5 \
+ !constraints { $rk != 2 && $rk != 0; }
+vreplve_d LSX 0111 00010010 00111 rk:5 vj:5 vd:5 \
+ !constraints { $rk != 2 && $rk != 0; }
+
+vreplvei_b LSX 0111 00101111 01111 0 imm:4 vj:5 vd:5
+vreplvei_h LSX 0111 00101111 01111 10 imm:3 vj:5 vd:5
+vreplvei_w LSX 0111 00101111 01111 110 imm:2 vj:5 vd:5
+vreplvei_d LSX 0111 00101111 01111 1110 imm:1 vj:5 vd:5
+
+vbsll_v LSX 0111 00101000 11100 imm:5 vj:5 vd:5
+vbsrl_v LSX 0111 00101000 11101 imm:5 vj:5 vd:5
+
+vpackev_b LSX 0111 00010001 01100 vk:5 vj:5 vd:5
+vpackev_h LSX 0111 00010001 01101 vk:5 vj:5 vd:5
+vpackev_w LSX 0111 00010001 01110 vk:5 vj:5 vd:5
+vpackev_d LSX 0111 00010001 01111 vk:5 vj:5 vd:5
+vpackod_b LSX 0111 00010001 10000 vk:5 vj:5 vd:5
+vpackod_h LSX 0111 00010001 10001 vk:5 vj:5 vd:5
+vpackod_w LSX 0111 00010001 10010 vk:5 vj:5 vd:5
+vpackod_d LSX 0111 00010001 10011 vk:5 vj:5 vd:5
+
+vpickev_b LSX 0111 00010001 11100 vk:5 vj:5 vd:5
+vpickev_h LSX 0111 00010001 11101 vk:5 vj:5 vd:5
+vpickev_w LSX 0111 00010001 11110 vk:5 vj:5 vd:5
+vpickev_d LSX 0111 00010001 11111 vk:5 vj:5 vd:5
+vpickod_b LSX 0111 00010010 00000 vk:5 vj:5 vd:5
+vpickod_h LSX 0111 00010010 00001 vk:5 vj:5 vd:5
+vpickod_w LSX 0111 00010010 00010 vk:5 vj:5 vd:5
+vpickod_d LSX 0111 00010010 00011 vk:5 vj:5 vd:5
+
+vilvl_b LSX 0111 00010001 10100 vk:5 vj:5 vd:5
+vilvl_h LSX 0111 00010001 10101 vk:5 vj:5 vd:5
+vilvl_w LSX 0111 00010001 10110 vk:5 vj:5 vd:5
+vilvl_d LSX 0111 00010001 10111 vk:5 vj:5 vd:5
+vilvh_b LSX 0111 00010001 11000 vk:5 vj:5 vd:5
+vilvh_h LSX 0111 00010001 11001 vk:5 vj:5 vd:5
+vilvh_w LSX 0111 00010001 11010 vk:5 vj:5 vd:5
+vilvh_d LSX 0111 00010001 11011 vk:5 vj:5 vd:5
+
+vshuf4i_b LSX 0111 00111001 00 imm:8 vj:5 vd:5
+vshuf4i_h LSX 0111 00111001 01 imm:8 vj:5 vd:5
+vshuf4i_w LSX 0111 00111001 10 imm:8 vj:5 vd:5
+vshuf4i_d LSX 0111 00111001 11 imm:8 vj:5 vd:5
+
+vpermi_w LSX 0111 00111110 01 imm:8 vj:5 vd:5
+
+vextrins_d LSX 0111 00111000 00 imm:8 vj:5 vd:5
+vextrins_w LSX 0111 00111000 01 imm:8 vj:5 vd:5
+vextrins_h LSX 0111 00111000 10 imm:8 vj:5 vd:5
+vextrins_b LSX 0111 00111000 11 imm:8 vj:5 vd:5
+
+vld LSX 0010 110000 si12:12 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+vst LSX 0010 110001 si12:12 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+vldx LSX 0011 10000100 00000 rk:5 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != $rk && $rk != 2 && $rj != 2; } \
+ !memory { reg_plus_reg($rj, $rk); }
+vstx LSX 0011 10000100 01000 rk:5 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != $rk && $rk != 2 && $rj != 2; } \
+ !memory { reg_plus_reg($rj, $rk); }
+
+vldrepl_d LSX 0011 00000001 0 si9:9 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si9, 9) * 8); }
+vldrepl_w LSX 0011 00000010 si10:10 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si10, 10) * 4); }
+vldrepl_h LSX 0011 0000010 si11:11 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si11, 11) * 2); }
+vldrepl_b LSX 0011 000010 si12:12 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+
+vstelm_d LSX 0011 00010001 0 si1:1 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 8); }
+vstelm_w LSX 0011 00010010 si2:2 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 4); }
+vstelm_h LSX 0011 0001010 si3:3 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 2); }
+vstelm_b LSX 0011 000110 si4:4 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8)); }
+
+vldi LSX 0111 00111110 00 si13:13 vd:5 \
+ !constraints { $si13 >= 0 && $si13 <= 12; }
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [risu PATCH 2/5] loongarch: Add LASX instructions
2023-10-25 9:29 [risu PATCH 0/5] Add LoongArch LSX/LASX instructions Song Gao
2023-10-25 9:29 ` [risu PATCH 1/5] loongarch: Add LSX instructions Song Gao
@ 2023-10-25 9:29 ` Song Gao
2023-10-25 9:29 ` [risu PATCH 3/5] loongarch: reginfo suport LSX/LASX Song Gao
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Song Gao @ 2023-10-25 9:29 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
loongarch64.risu | 815 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 815 insertions(+)
diff --git a/loongarch64.risu b/loongarch64.risu
index 78ccee3..596de90 100644
--- a/loongarch64.risu
+++ b/loongarch64.risu
@@ -1417,3 +1417,818 @@ vstelm_b LSX 0011 000110 si4:4 si8:8 rj:5 vd:5 \
vldi LSX 0111 00111110 00 si13:13 vd:5 \
!constraints { $si13 >= 0 && $si13 <= 12; }
+
+#
+# LASX instructions
+#
+
+xvadd_b LASX 0111 01000000 10100 vk:5 vj:5 vd:5
+xvadd_h LASX 0111 01000000 10101 vk:5 vj:5 vd:5
+xvadd_w LASX 0111 01000000 10110 vk:5 vj:5 vd:5
+xvadd_d LASX 0111 01000000 10111 vk:5 vj:5 vd:5
+xvadd_q LASX 0111 01010010 11010 vk:5 vj:5 vd:5
+xvsub_b LASX 0111 01000000 11000 vk:5 vj:5 vd:5
+xvsub_h LASX 0111 01000000 11001 vk:5 vj:5 vd:5
+xvsub_w LASX 0111 01000000 11010 vk:5 vj:5 vd:5
+xvsub_d LASX 0111 01000000 11011 vk:5 vj:5 vd:5
+xvsub_q LASX 0111 01010010 11011 vk:5 vj:5 vd:5
+
+xvaddi_bu LASX 0111 01101000 10100 imm:5 vj:5 vd:5
+xvaddi_hu LASX 0111 01101000 10101 imm:5 vj:5 vd:5
+xvaddi_wu LASX 0111 01101000 10110 imm:5 vj:5 vd:5
+xvaddi_du LASX 0111 01101000 10111 imm:5 vj:5 vd:5
+xvsubi_bu LASX 0111 01101000 11000 imm:5 vj:5 vd:5
+xvsubi_hu LASX 0111 01101000 11001 imm:5 vj:5 vd:5
+xvsubi_wu LASX 0111 01101000 11010 imm:5 vj:5 vd:5
+xvsubi_du LASX 0111 01101000 11011 imm:5 vj:5 vd:5
+
+xvneg_b LASX 0111 01101001 11000 01100 vj:5 vd:5
+xvneg_h LASX 0111 01101001 11000 01101 vj:5 vd:5
+xvneg_w LASX 0111 01101001 11000 01110 vj:5 vd:5
+xvneg_d LASX 0111 01101001 11000 01111 vj:5 vd:5
+
+xvsadd_b LASX 0111 01000100 01100 vk:5 vj:5 vd:5
+xvsadd_h LASX 0111 01000100 01101 vk:5 vj:5 vd:5
+xvsadd_w LASX 0111 01000100 01110 vk:5 vj:5 vd:5
+xvsadd_d LASX 0111 01000100 01111 vk:5 vj:5 vd:5
+xvsadd_bu LASX 0111 01000100 10100 vk:5 vj:5 vd:5
+xvsadd_hu LASX 0111 01000100 10101 vk:5 vj:5 vd:5
+xvsadd_wu LASX 0111 01000100 10110 vk:5 vj:5 vd:5
+xvsadd_du LASX 0111 01000100 10111 vk:5 vj:5 vd:5
+
+xvssub_b LASX 0111 01000100 10000 vk:5 vj:5 vd:5
+xvssub_h LASX 0111 01000100 10001 vk:5 vj:5 vd:5
+xvssub_w LASX 0111 01000100 10010 vk:5 vj:5 vd:5
+xvssub_d LASX 0111 01000100 10011 vk:5 vj:5 vd:5
+xvssub_bu LASX 0111 01000100 11000 vk:5 vj:5 vd:5
+xvssub_hu LASX 0111 01000100 11001 vk:5 vj:5 vd:5
+xvssub_wu LASX 0111 01000100 11010 vk:5 vj:5 vd:5
+xvssub_du LASX 0111 01000100 11011 vk:5 vj:5 vd:5
+
+xvhaddw_h_b LASX 0111 01000101 01000 vk:5 vj:5 vd:5
+xvhaddw_w_h LASX 0111 01000101 01001 vk:5 vj:5 vd:5
+xvhaddw_d_w LASX 0111 01000101 01010 vk:5 vj:5 vd:5
+xvhaddw_q_d LASX 0111 01000101 01011 vk:5 vj:5 vd:5
+xvhaddw_hu_bu LASX 0111 01000101 10000 vk:5 vj:5 vd:5
+xvhaddw_wu_hu LASX 0111 01000101 10001 vk:5 vj:5 vd:5
+xvhaddw_du_wu LASX 0111 01000101 10010 vk:5 vj:5 vd:5
+xvhaddw_qu_du LASX 0111 01000101 10011 vk:5 vj:5 vd:5
+
+xvhsubw_h_b LASX 0111 01000101 01100 vk:5 vj:5 vd:5
+xvhsubw_w_h LASX 0111 01000101 01101 vk:5 vj:5 vd:5
+xvhsubw_d_w LASX 0111 01000101 01110 vk:5 vj:5 vd:5
+xvhsubw_q_d LASX 0111 01000101 01111 vk:5 vj:5 vd:5
+xvhsubw_hu_bu LASX 0111 01000101 10100 vk:5 vj:5 vd:5
+xvhsubw_wu_hu LASX 0111 01000101 10101 vk:5 vj:5 vd:5
+xvhsubw_du_wu LASX 0111 01000101 10110 vk:5 vj:5 vd:5
+xvhsubw_qu_du LASX 0111 01000101 10111 vk:5 vj:5 vd:5
+
+xvaddwev_h_b LASX 0111 01000001 11100 vk:5 vj:5 vd:5
+xvaddwev_w_h LASX 0111 01000001 11101 vk:5 vj:5 vd:5
+xvaddwev_d_w LASX 0111 01000001 11110 vk:5 vj:5 vd:5
+xvaddwev_q_d LASX 0111 01000001 11111 vk:5 vj:5 vd:5
+xvaddwod_h_b LASX 0111 01000010 00100 vk:5 vj:5 vd:5
+xvaddwod_w_h LASX 0111 01000010 00101 vk:5 vj:5 vd:5
+xvaddwod_d_w LASX 0111 01000010 00110 vk:5 vj:5 vd:5
+xvaddwod_q_d LASX 0111 01000010 00111 vk:5 vj:5 vd:5
+
+xvsubwev_h_b LASX 0111 01000010 00000 vk:5 vj:5 vd:5
+xvsubwev_w_h LASX 0111 01000010 00001 vk:5 vj:5 vd:5
+xvsubwev_d_w LASX 0111 01000010 00010 vk:5 vj:5 vd:5
+xvsubwev_q_d LASX 0111 01000010 00011 vk:5 vj:5 vd:5
+xvsubwod_h_b LASX 0111 01000010 01000 vk:5 vj:5 vd:5
+xvsubwod_w_h LASX 0111 01000010 01001 vk:5 vj:5 vd:5
+xvsubwod_d_w LASX 0111 01000010 01010 vk:5 vj:5 vd:5
+xvsubwod_q_d LASX 0111 01000010 01011 vk:5 vj:5 vd:5
+
+xvaddwev_h_bu LASX 0111 01000010 11100 vk:5 vj:5 vd:5
+xvaddwev_w_hu LASX 0111 01000010 11101 vk:5 vj:5 vd:5
+xvaddwev_d_wu LASX 0111 01000010 11110 vk:5 vj:5 vd:5
+xvaddwev_q_du LASX 0111 01000010 11111 vk:5 vj:5 vd:5
+xvaddwod_h_bu LASX 0111 01000011 00100 vk:5 vj:5 vd:5
+xvaddwod_w_hu LASX 0111 01000011 00101 vk:5 vj:5 vd:5
+xvaddwod_d_wu LASX 0111 01000011 00110 vk:5 vj:5 vd:5
+xvaddwod_q_du LASX 0111 01000011 00111 vk:5 vj:5 vd:5
+
+xvsubwev_h_bu LASX 0111 01000011 00000 vk:5 vj:5 vd:5
+xvsubwev_w_hu LASX 0111 01000011 00001 vk:5 vj:5 vd:5
+xvsubwev_d_wu LASX 0111 01000011 00010 vk:5 vj:5 vd:5
+xvsubwev_q_du LASX 0111 01000011 00011 vk:5 vj:5 vd:5
+xvsubwod_h_bu LASX 0111 01000011 01000 vk:5 vj:5 vd:5
+xvsubwod_w_hu LASX 0111 01000011 01001 vk:5 vj:5 vd:5
+xvsubwod_d_wu LASX 0111 01000011 01010 vk:5 vj:5 vd:5
+xvsubwod_q_du LASX 0111 01000011 01011 vk:5 vj:5 vd:5
+
+xvaddwev_h_bu_b LASX 0111 01000011 11100 vk:5 vj:5 vd:5
+xvaddwev_w_hu_h LASX 0111 01000011 11101 vk:5 vj:5 vd:5
+xvaddwev_d_wu_w LASX 0111 01000011 11110 vk:5 vj:5 vd:5
+xvaddwev_q_du_d LASX 0111 01000011 11111 vk:5 vj:5 vd:5
+xvaddwod_h_bu_b LASX 0111 01000100 00000 vk:5 vj:5 vd:5
+xvaddwod_w_hu_h LASX 0111 01000100 00001 vk:5 vj:5 vd:5
+xvaddwod_d_wu_w LASX 0111 01000100 00010 vk:5 vj:5 vd:5
+xvaddwod_q_du_d LASX 0111 01000100 00011 vk:5 vj:5 vd:5
+
+xvavg_b LASX 0111 01000110 01000 vk:5 vj:5 vd:5
+xvavg_h LASX 0111 01000110 01001 vk:5 vj:5 vd:5
+xvavg_w LASX 0111 01000110 01010 vk:5 vj:5 vd:5
+xvavg_d LASX 0111 01000110 01011 vk:5 vj:5 vd:5
+xvavg_bu LASX 0111 01000110 01100 vk:5 vj:5 vd:5
+xvavg_hu LASX 0111 01000110 01101 vk:5 vj:5 vd:5
+xvavg_wu LASX 0111 01000110 01110 vk:5 vj:5 vd:5
+xvavg_du LASX 0111 01000110 01111 vk:5 vj:5 vd:5
+xvavgr_b LASX 0111 01000110 10000 vk:5 vj:5 vd:5
+xvavgr_h LASX 0111 01000110 10001 vk:5 vj:5 vd:5
+xvavgr_w LASX 0111 01000110 10010 vk:5 vj:5 vd:5
+xvavgr_d LASX 0111 01000110 10011 vk:5 vj:5 vd:5
+xvavgr_bu LASX 0111 01000110 10100 vk:5 vj:5 vd:5
+xvavgr_hu LASX 0111 01000110 10101 vk:5 vj:5 vd:5
+xvavgr_wu LASX 0111 01000110 10110 vk:5 vj:5 vd:5
+xvavgr_du LASX 0111 01000110 10111 vk:5 vj:5 vd:5
+
+xvabsd_b LASX 0111 01000110 00000 vk:5 vj:5 vd:5
+xvabsd_h LASX 0111 01000110 00001 vk:5 vj:5 vd:5
+xvabsd_w LASX 0111 01000110 00010 vk:5 vj:5 vd:5
+xvabsd_d LASX 0111 01000110 00011 vk:5 vj:5 vd:5
+xvabsd_bu LASX 0111 01000110 00100 vk:5 vj:5 vd:5
+xvabsd_hu LASX 0111 01000110 00101 vk:5 vj:5 vd:5
+xvabsd_wu LASX 0111 01000110 00110 vk:5 vj:5 vd:5
+xvabsd_du LASX 0111 01000110 00111 vk:5 vj:5 vd:5
+
+xvadda_b LASX 0111 01000101 11000 vk:5 vj:5 vd:5
+xvadda_h LASX 0111 01000101 11001 vk:5 vj:5 vd:5
+xvadda_w LASX 0111 01000101 11010 vk:5 vj:5 vd:5
+xvadda_d LASX 0111 01000101 11011 vk:5 vj:5 vd:5
+
+xvmax_b LASX 0111 01000111 00000 vk:5 vj:5 vd:5
+xvmax_h LASX 0111 01000111 00001 vk:5 vj:5 vd:5
+xvmax_w LASX 0111 01000111 00010 vk:5 vj:5 vd:5
+xvmax_d LASX 0111 01000111 00011 vk:5 vj:5 vd:5
+xvmax_bu LASX 0111 01000111 01000 vk:5 vj:5 vd:5
+xvmax_hu LASX 0111 01000111 01001 vk:5 vj:5 vd:5
+xvmax_wu LASX 0111 01000111 01010 vk:5 vj:5 vd:5
+xvmax_du LASX 0111 01000111 01011 vk:5 vj:5 vd:5
+
+xvmaxi_b LASX 0111 01101001 00000 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmaxi_h LASX 0111 01101001 00001 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmaxi_w LASX 0111 01101001 00010 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmaxi_d LASX 0111 01101001 00011 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmaxi_bu LASX 0111 01101001 01000 imm:5 vj:5 vd:5
+xvmaxi_hu LASX 0111 01101001 01001 imm:5 vj:5 vd:5
+xvmaxi_wu LASX 0111 01101001 01010 imm:5 vj:5 vd:5
+xvmaxi_du LASX 0111 01101001 01011 imm:5 vj:5 vd:5
+
+xvmin_b LASX 0111 01000111 00100 vk:5 vj:5 vd:5
+xvmin_h LASX 0111 01000111 00101 vk:5 vj:5 vd:5
+xvmin_w LASX 0111 01000111 00110 vk:5 vj:5 vd:5
+xvmin_d LASX 0111 01000111 00111 vk:5 vj:5 vd:5
+xvmin_bu LASX 0111 01000111 01100 vk:5 vj:5 vd:5
+xvmin_hu LASX 0111 01000111 01101 vk:5 vj:5 vd:5
+xvmin_wu LASX 0111 01000111 01110 vk:5 vj:5 vd:5
+xvmin_du LASX 0111 01000111 01111 vk:5 vj:5 vd:5
+
+xvmini_b LASX 0111 01101001 00100 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmini_h LASX 0111 01101001 00101 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmini_w LASX 0111 01101001 00110 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmini_d LASX 0111 01101001 00111 imm:5 vj:5 vd:5 \
+ !constraints { $imm = sextract($imm, 5);}
+xvmini_bu LASX 0111 01101001 01100 imm:5 vj:5 vd:5
+xvmini_hu LASX 0111 01101001 01101 imm:5 vj:5 vd:5
+xvmini_wu LASX 0111 01101001 01110 imm:5 vj:5 vd:5
+xvmini_du LASX 0111 01101001 01111 imm:5 vj:5 vd:5
+
+xvmul_b LASX 0111 01001000 01000 vk:5 vj:5 vd:5
+xvmul_h LASX 0111 01001000 01001 vk:5 vj:5 vd:5
+xvmul_w LASX 0111 01001000 01010 vk:5 vj:5 vd:5
+xvmul_d LASX 0111 01001000 01011 vk:5 vj:5 vd:5
+xvmuh_b LASX 0111 01001000 01100 vk:5 vj:5 vd:5
+xvmuh_h LASX 0111 01001000 01101 vk:5 vj:5 vd:5
+xvmuh_w LASX 0111 01001000 01110 vk:5 vj:5 vd:5
+xvmuh_d LASX 0111 01001000 01111 vk:5 vj:5 vd:5
+xvmuh_bu LASX 0111 01001000 10000 vk:5 vj:5 vd:5
+xvmuh_hu LASX 0111 01001000 10001 vk:5 vj:5 vd:5
+xvmuh_wu LASX 0111 01001000 10010 vk:5 vj:5 vd:5
+xvmuh_du LASX 0111 01001000 10011 vk:5 vj:5 vd:5
+
+xvmulwev_h_b LASX 0111 01001001 00000 vk:5 vj:5 vd:5
+xvmulwev_w_h LASX 0111 01001001 00001 vk:5 vj:5 vd:5
+xvmulwev_d_w LASX 0111 01001001 00010 vk:5 vj:5 vd:5
+xvmulwev_q_d LASX 0111 01001001 00011 vk:5 vj:5 vd:5
+xvmulwod_h_b LASX 0111 01001001 00100 vk:5 vj:5 vd:5
+xvmulwod_w_h LASX 0111 01001001 00101 vk:5 vj:5 vd:5
+xvmulwod_d_w LASX 0111 01001001 00110 vk:5 vj:5 vd:5
+xvmulwod_q_d LASX 0111 01001001 00111 vk:5 vj:5 vd:5
+xvmulwev_h_bu LASX 0111 01001001 10000 vk:5 vj:5 vd:5
+xvmulwev_w_hu LASX 0111 01001001 10001 vk:5 vj:5 vd:5
+xvmulwev_d_wu LASX 0111 01001001 10010 vk:5 vj:5 vd:5
+xvmulwev_q_du LASX 0111 01001001 10011 vk:5 vj:5 vd:5
+xvmulwod_h_bu LASX 0111 01001001 10100 vk:5 vj:5 vd:5
+xvmulwod_w_hu LASX 0111 01001001 10101 vk:5 vj:5 vd:5
+xvmulwod_d_wu LASX 0111 01001001 10110 vk:5 vj:5 vd:5
+xvmulwod_q_du LASX 0111 01001001 10111 vk:5 vj:5 vd:5
+xvmulwev_h_bu_b LASX 0111 01001010 00000 vk:5 vj:5 vd:5
+xvmulwev_w_hu_h LASX 0111 01001010 00001 vk:5 vj:5 vd:5
+xvmulwev_d_wu_w LASX 0111 01001010 00010 vk:5 vj:5 vd:5
+xvmulwev_q_du_d LASX 0111 01001010 00011 vk:5 vj:5 vd:5
+xvmulwod_h_bu_b LASX 0111 01001010 00100 vk:5 vj:5 vd:5
+xvmulwod_w_hu_h LASX 0111 01001010 00101 vk:5 vj:5 vd:5
+xvmulwod_d_wu_w LASX 0111 01001010 00110 vk:5 vj:5 vd:5
+xvmulwod_q_du_d LASX 0111 01001010 00111 vk:5 vj:5 vd:5
+
+xvmadd_b LASX 0111 01001010 10000 vk:5 vj:5 vd:5
+xvmadd_h LASX 0111 01001010 10001 vk:5 vj:5 vd:5
+xvmadd_w LASX 0111 01001010 10010 vk:5 vj:5 vd:5
+xvmadd_d LASX 0111 01001010 10011 vk:5 vj:5 vd:5
+xvmsub_b LASX 0111 01001010 10100 vk:5 vj:5 vd:5
+xvmsub_h LASX 0111 01001010 10101 vk:5 vj:5 vd:5
+xvmsub_w LASX 0111 01001010 10110 vk:5 vj:5 vd:5
+xvmsub_d LASX 0111 01001010 10111 vk:5 vj:5 vd:5
+
+xvmaddwev_h_b LASX 0111 01001010 11000 vk:5 vj:5 vd:5
+xvmaddwev_w_h LASX 0111 01001010 11001 vk:5 vj:5 vd:5
+xvmaddwev_d_w LASX 0111 01001010 11010 vk:5 vj:5 vd:5
+xvmaddwev_q_d LASX 0111 01001010 11011 vk:5 vj:5 vd:5
+xvmaddwod_h_b LASX 0111 01001010 11100 vk:5 vj:5 vd:5
+xvmaddwod_w_h LASX 0111 01001010 11101 vk:5 vj:5 vd:5
+xvmaddwod_d_w LASX 0111 01001010 11110 vk:5 vj:5 vd:5
+xvmaddwod_q_d LASX 0111 01001010 11111 vk:5 vj:5 vd:5
+xvmaddwev_h_bu LASX 0111 01001011 01000 vk:5 vj:5 vd:5
+xvmaddwev_w_hu LASX 0111 01001011 01001 vk:5 vj:5 vd:5
+xvmaddwev_d_wu LASX 0111 01001011 01010 vk:5 vj:5 vd:5
+xvmaddwev_q_du LASX 0111 01001011 01011 vk:5 vj:5 vd:5
+xvmaddwod_h_bu LASX 0111 01001011 01100 vk:5 vj:5 vd:5
+xvmaddwod_w_hu LASX 0111 01001011 01101 vk:5 vj:5 vd:5
+xvmaddwod_d_wu LASX 0111 01001011 01110 vk:5 vj:5 vd:5
+xvmaddwod_q_du LASX 0111 01001011 01111 vk:5 vj:5 vd:5
+xvmaddwev_h_bu_b LASX 0111 01001011 11000 vk:5 vj:5 vd:5
+xvmaddwev_w_hu_h LASX 0111 01001011 11001 vk:5 vj:5 vd:5
+xvmaddwev_d_wu_w LASX 0111 01001011 11010 vk:5 vj:5 vd:5
+xvmaddwev_q_du_d LASX 0111 01001011 11011 vk:5 vj:5 vd:5
+xvmaddwod_h_bu_b LASX 0111 01001011 11100 vk:5 vj:5 vd:5
+xvmaddwod_w_hu_h LASX 0111 01001011 11101 vk:5 vj:5 vd:5
+xvmaddwod_d_wu_w LASX 0111 01001011 11110 vk:5 vj:5 vd:5
+xvmaddwod_q_du_d LASX 0111 01001011 11111 vk:5 vj:5 vd:5
+
+xvdiv_b LASX 0111 01001110 00000 vk:5 vj:5 vd:5
+xvdiv_h LASX 0111 01001110 00001 vk:5 vj:5 vd:5
+xvdiv_w LASX 0111 01001110 00010 vk:5 vj:5 vd:5
+xvdiv_d LASX 0111 01001110 00011 vk:5 vj:5 vd:5
+xvmod_b LASX 0111 01001110 00100 vk:5 vj:5 vd:5
+xvmod_h LASX 0111 01001110 00101 vk:5 vj:5 vd:5
+xvmod_w LASX 0111 01001110 00110 vk:5 vj:5 vd:5
+xvmod_d LASX 0111 01001110 00111 vk:5 vj:5 vd:5
+xvdiv_bu LASX 0111 01001110 01000 vk:5 vj:5 vd:5
+xvdiv_hu LASX 0111 01001110 01001 vk:5 vj:5 vd:5
+xvdiv_wu LASX 0111 01001110 01010 vk:5 vj:5 vd:5
+xvdiv_du LASX 0111 01001110 01011 vk:5 vj:5 vd:5
+xvmod_bu LASX 0111 01001110 01100 vk:5 vj:5 vd:5
+xvmod_hu LASX 0111 01001110 01101 vk:5 vj:5 vd:5
+xvmod_wu LASX 0111 01001110 01110 vk:5 vj:5 vd:5
+xvmod_du LASX 0111 01001110 01111 vk:5 vj:5 vd:5
+
+xvsat_b LASX 0111 01110010 01000 01 imm:3 vj:5 vd:5
+xvsat_h LASX 0111 01110010 01000 1 imm:4 vj:5 vd:5
+xvsat_w LASX 0111 01110010 01001 imm:5 vj:5 vd:5
+xvsat_d LASX 0111 01110010 0101 imm:6 vj:5 vd:5
+xvsat_bu LASX 0111 01110010 10000 01 imm:3 vj:5 vd:5
+xvsat_hu LASX 0111 01110010 10000 1 imm:4 vj:5 vd:5
+xvsat_wu LASX 0111 01110010 10001 imm:5 vj:5 vd:5
+xvsat_du LASX 0111 01110010 1001 imm:6 vj:5 vd:5
+
+xvexth_h_b LASX 0111 01101001 11101 11000 vj:5 vd:5
+xvexth_w_h LASX 0111 01101001 11101 11001 vj:5 vd:5
+xvexth_d_w LASX 0111 01101001 11101 11010 vj:5 vd:5
+xvexth_q_d LASX 0111 01101001 11101 11011 vj:5 vd:5
+xvexth_hu_bu LASX 0111 01101001 11101 11100 vj:5 vd:5
+xvexth_wu_hu LASX 0111 01101001 11101 11101 vj:5 vd:5
+xvexth_du_wu LASX 0111 01101001 11101 11110 vj:5 vd:5
+xvexth_qu_du LASX 0111 01101001 11101 11111 vj:5 vd:5
+
+vext2xv_h_b LASX 0111 01101001 11110 00100 vj:5 vd:5
+vext2xv_w_b LASX 0111 01101001 11110 00101 vj:5 vd:5
+vext2xv_d_b LASX 0111 01101001 11110 00110 vj:5 vd:5
+vext2xv_w_h LASX 0111 01101001 11110 00111 vj:5 vd:5
+vext2xv_d_h LASX 0111 01101001 11110 01000 vj:5 vd:5
+vext2xv_d_w LASX 0111 01101001 11110 01001 vj:5 vd:5
+vext2xv_hu_bu LASX 0111 01101001 11110 01010 vj:5 vd:5
+vext2xv_wu_bu LASX 0111 01101001 11110 01011 vj:5 vd:5
+vext2xv_du_bu LASX 0111 01101001 11110 01100 vj:5 vd:5
+vext2xv_wu_hu LASX 0111 01101001 11110 01101 vj:5 vd:5
+vext2xv_du_hu LASX 0111 01101001 11110 01110 vj:5 vd:5
+vext2xv_du_wu LASX 0111 01101001 11110 01111 vj:5 vd:5
+
+xvsigncov_b LASX 0111 01010010 11100 vk:5 vj:5 vd:5
+xvsigncov_h LASX 0111 01010010 11101 vk:5 vj:5 vd:5
+xvsigncov_w LASX 0111 01010010 11110 vk:5 vj:5 vd:5
+xvsigncov_d LASX 0111 01010010 11111 vk:5 vj:5 vd:5
+
+xvmskltz_b LASX 0111 01101001 11000 10000 vj:5 vd:5
+xvmskltz_h LASX 0111 01101001 11000 10001 vj:5 vd:5
+xvmskltz_w LASX 0111 01101001 11000 10010 vj:5 vd:5
+xvmskltz_d LASX 0111 01101001 11000 10011 vj:5 vd:5
+xvmskgez_b LASX 0111 01101001 11000 10100 vj:5 vd:5
+xvmsknz_b LASX 0111 01101001 11000 11000 vj:5 vd:5
+
+xvldi LASX 0111 01111110 00 si13:13 vd:5 \
+ !constraints { $si13 >= 0 && $si13 <= 12; }
+
+xvand_v LASX 0111 01010010 01100 vk:5 vj:5 vd:5
+xvor_v LASX 0111 01010010 01101 vk:5 vj:5 vd:5
+xvxor_v LASX 0111 01010010 01110 vk:5 vj:5 vd:5
+xvnor_v LASX 0111 01010010 01111 vk:5 vj:5 vd:5
+xvandn_v LASX 0111 01010010 10000 vk:5 vj:5 vd:5
+xvorn_v LASX 0111 01010010 10001 vk:5 vj:5 vd:5
+
+xvandi_b LASX 0111 01111101 00 imm:8 vj:5 vd:5
+xvori_b LASX 0111 01111101 01 imm:8 vj:5 vd:5
+xvxori_b LASX 0111 01111101 10 imm:8 vj:5 vd:5
+xvnori_b LASX 0111 01111101 11 imm:8 vj:5 vd:5
+
+xvsll_b LASX 0111 01001110 10000 vk:5 vj:5 vd:5
+xvsll_h LASX 0111 01001110 10001 vk:5 vj:5 vd:5
+xvsll_w LASX 0111 01001110 10010 vk:5 vj:5 vd:5
+xvsll_d LASX 0111 01001110 10011 vk:5 vj:5 vd:5
+xvslli_b LASX 0111 01110010 11000 01 imm:3 vj:5 vd:5
+xvslli_h LASX 0111 01110010 11000 1 imm:4 vj:5 vd:5
+xvslli_w LASX 0111 01110010 11001 imm:5 vj:5 vd:5
+xvslli_d LASX 0111 01110010 1101 imm:6 vj:5 vd:5
+xvsrl_b LASX 0111 01001110 10100 vk:5 vj:5 vd:5
+xvsrl_h LASX 0111 01001110 10101 vk:5 vj:5 vd:5
+xvsrl_w LASX 0111 01001110 10110 vk:5 vj:5 vd:5
+xvsrl_d LASX 0111 01001110 10111 vk:5 vj:5 vd:5
+xvsrli_b LASX 0111 01110011 00000 01 imm:3 vj:5 vd:5
+xvsrli_h LASX 0111 01110011 00000 1 imm:4 vj:5 vd:5
+xvsrli_w LASX 0111 01110011 00001 imm:5 vj:5 vd:5
+xvsrli_d LASX 0111 01110011 0001 imm:6 vj:5 vd:5
+xvsra_b LASX 0111 01001110 11000 vk:5 vj:5 vd:5
+xvsra_h LASX 0111 01001110 11001 vk:5 vj:5 vd:5
+xvsra_w LASX 0111 01001110 11010 vk:5 vj:5 vd:5
+xvsra_d LASX 0111 01001110 11011 vk:5 vj:5 vd:5
+xvsrai_b LASX 0111 01110011 01000 01 imm:3 vj:5 vd:5
+xvsrai_h LASX 0111 01110011 01000 1 imm:4 vj:5 vd:5
+xvsrai_w LASX 0111 01110011 01001 imm:5 vj:5 vd:5
+xvsrai_d LASX 0111 01110011 0101 imm:6 vj:5 vd:5
+xvrotr_b LASX 0111 01001110 11100 vk:5 vj:5 vd:5
+xvrotr_h LASX 0111 01001110 11101 vk:5 vj:5 vd:5
+xvrotr_w LASX 0111 01001110 11110 vk:5 vj:5 vd:5
+xvrotr_d LASX 0111 01001110 11111 vk:5 vj:5 vd:5
+xvrotri_b LASX 0111 01101010 00000 01 imm:3 vj:5 vd:5
+xvrotri_h LASX 0111 01101010 00000 1 imm:4 vj:5 vd:5
+xvrotri_w LASX 0111 01101010 00001 imm:5 vj:5 vd:5
+xvrotri_d LASX 0111 01101010 0001 imm:6 vj:5 vd:5
+
+xvsllwil_h_b LASX 0111 01110000 10000 01 imm:3 vj:5 vd:5
+xvsllwil_w_h LASX 0111 01110000 10000 1 imm:4 vj:5 vd:5
+xvsllwil_d_w LASX 0111 01110000 10001 imm:5 vj:5 vd:5
+xvextl_q_d LASX 0111 01110000 10010 00000 vj:5 vd:5
+xvsllwil_hu_bu LASX 0111 01110000 11000 01 imm:3 vj:5 vd:5
+xvsllwil_wu_hu LASX 0111 01110000 11000 1 imm:4 vj:5 vd:5
+xvsllwil_du_wu LASX 0111 01110000 11001 imm:5 vj:5 vd:5
+xvextl_qu_du LASX 0111 01110000 11010 00000 vj:5 vd:5
+
+xvsrlr_b LASX 0111 01001111 00000 vk:5 vj:5 vd:5
+xvsrlr_h LASX 0111 01001111 00001 vk:5 vj:5 vd:5
+xvsrlr_w LASX 0111 01001111 00010 vk:5 vj:5 vd:5
+xvsrlr_d LASX 0111 01001111 00011 vk:5 vj:5 vd:5
+xvsrlri_b LASX 0111 01101010 01000 01 imm:3 vj:5 vd:5
+xvsrlri_h LASX 0111 01101010 01000 1 imm:4 vj:5 vd:5
+xvsrlri_w LASX 0111 01101010 01001 imm:5 vj:5 vd:5
+xvsrlri_d LASX 0111 01101010 0101 imm:6 vj:5 vd:5
+xvsrar_b LASX 0111 01001111 00100 vk:5 vj:5 vd:5
+xvsrar_h LASX 0111 01001111 00101 vk:5 vj:5 vd:5
+xvsrar_w LASX 0111 01001111 00110 vk:5 vj:5 vd:5
+xvsrar_d LASX 0111 01001111 00111 vk:5 vj:5 vd:5
+xvsrari_b LASX 0111 01101010 10000 01 imm:3 vj:5 vd:5
+xvsrari_h LASX 0111 01101010 10000 1 imm:4 vj:5 vd:5
+xvsrari_w LASX 0111 01101010 10001 imm:5 vj:5 vd:5
+xvsrari_d LASX 0111 01101010 1001 imm:6 vj:5 vd:5
+
+xvsrln_b_h LASX 0111 01001111 01001 vk:5 vj:5 vd:5
+xvsrln_h_w LASX 0111 01001111 01010 vk:5 vj:5 vd:5
+xvsrln_w_d LASX 0111 01001111 01011 vk:5 vj:5 vd:5
+xvsran_b_h LASX 0111 01001111 01101 vk:5 vj:5 vd:5
+xvsran_h_w LASX 0111 01001111 01110 vk:5 vj:5 vd:5
+xvsran_w_d LASX 0111 01001111 01111 vk:5 vj:5 vd:5
+
+xvsrlni_b_h LASX 0111 01110100 00000 1 imm:4 vj:5 vd:5
+xvsrlni_h_w LASX 0111 01110100 00001 imm:5 vj:5 vd:5
+xvsrlni_w_d LASX 0111 01110100 0001 imm:6 vj:5 vd:5
+xvsrlni_d_q LASX 0111 01110100 001 imm:7 vj:5 vd:5
+xvsrani_b_h LASX 0111 01110101 10000 1 imm:4 vj:5 vd:5
+xvsrani_h_w LASX 0111 01110101 10001 imm:5 vj:5 vd:5
+xvsrani_w_d LASX 0111 01110101 1001 imm:6 vj:5 vd:5
+xvsrani_d_q LASX 0111 01110101 101 imm:7 vj:5 vd:5
+
+xvsrlrn_b_h LASX 0111 01001111 10001 vk:5 vj:5 vd:5
+xvsrlrn_h_w LASX 0111 01001111 10010 vk:5 vj:5 vd:5
+xvsrlrn_w_d LASX 0111 01001111 10011 vk:5 vj:5 vd:5
+xvsrarn_b_h LASX 0111 01001111 10101 vk:5 vj:5 vd:5
+xvsrarn_h_w LASX 0111 01001111 10110 vk:5 vj:5 vd:5
+xvsrarn_w_d LASX 0111 01001111 10111 vk:5 vj:5 vd:5
+
+xvsrlrni_b_h LASX 0111 01110100 01000 1 imm:4 vj:5 vd:5
+xvsrlrni_h_w LASX 0111 01110100 01001 imm:5 vj:5 vd:5
+xvsrlrni_w_d LASX 0111 01110100 0101 imm:6 vj:5 vd:5
+xvsrlrni_d_q LASX 0111 01110100 011 imm:7 vj:5 vd:5
+xvsrarni_b_h LASX 0111 01110101 11000 1 imm:4 vj:5 vd:5
+xvsrarni_h_w LASX 0111 01110101 11001 imm:5 vj:5 vd:5
+xvsrarni_w_d LASX 0111 01110101 1101 imm:6 vj:5 vd:5
+xvsrarni_d_q LASX 0111 01110101 111 imm:7 vj:5 vd:5
+
+xvssrln_b_h LASX 0111 01001111 11001 vk:5 vj:5 vd:5
+xvssrln_h_w LASX 0111 01001111 11010 vk:5 vj:5 vd:5
+xvssrln_w_d LASX 0111 01001111 11011 vk:5 vj:5 vd:5
+xvssran_b_h LASX 0111 01001111 11101 vk:5 vj:5 vd:5
+xvssran_h_w LASX 0111 01001111 11110 vk:5 vj:5 vd:5
+xvssran_w_d LASX 0111 01001111 11111 vk:5 vj:5 vd:5
+xvssrln_bu_h LASX 0111 01010000 01001 vk:5 vj:5 vd:5
+xvssrln_hu_w LASX 0111 01010000 01010 vk:5 vj:5 vd:5
+xvssrln_wu_d LASX 0111 01010000 01011 vk:5 vj:5 vd:5
+xvssran_bu_h LASX 0111 01010000 01101 vk:5 vj:5 vd:5
+xvssran_hu_w LASX 0111 01010000 01110 vk:5 vj:5 vd:5
+xvssran_wu_d LASX 0111 01010000 01111 vk:5 vj:5 vd:5
+
+xvssrlni_b_h LASX 0111 01110100 10000 1 imm:4 vj:5 vd:5
+xvssrlni_h_w LASX 0111 01110100 10001 imm:5 vj:5 vd:5
+xvssrlni_w_d LASX 0111 01110100 1001 imm:6 vj:5 vd:5
+xvssrlni_d_q LASX 0111 01110100 101 imm:7 vj:5 vd:5
+xvssrani_b_h LASX 0111 01110110 00000 1 imm:4 vj:5 vd:5
+xvssrani_h_w LASX 0111 01110110 00001 imm:5 vj:5 vd:5
+xvssrani_w_d LASX 0111 01110110 0001 imm:6 vj:5 vd:5
+xvssrani_d_q LASX 0111 01110110 001 imm:7 vj:5 vd:5
+xvssrlni_bu_h LASX 0111 01110100 11000 1 imm:4 vj:5 vd:5
+xvssrlni_hu_w LASX 0111 01110100 11001 imm:5 vj:5 vd:5
+xvssrlni_wu_d LASX 0111 01110100 1101 imm:6 vj:5 vd:5
+xvssrlni_du_q LASX 0111 01110100 111 imm:7 vj:5 vd:5
+xvssrani_bu_h LASX 0111 01110110 01000 1 imm:4 vj:5 vd:5
+xvssrani_hu_w LASX 0111 01110110 01001 imm:5 vj:5 vd:5
+xvssrani_wu_d LASX 0111 01110110 0101 imm:6 vj:5 vd:5
+xvssrani_du_q LASX 0111 01110110 011 imm:7 vj:5 vd:5
+
+xvssrlrn_b_h LASX 0111 01010000 00001 vk:5 vj:5 vd:5
+xvssrlrn_h_w LASX 0111 01010000 00010 vk:5 vj:5 vd:5
+xvssrlrn_w_d LASX 0111 01010000 00011 vk:5 vj:5 vd:5
+xvssrarn_b_h LASX 0111 01010000 00101 vk:5 vj:5 vd:5
+xvssrarn_h_w LASX 0111 01010000 00110 vk:5 vj:5 vd:5
+xvssrarn_w_d LASX 0111 01010000 00111 vk:5 vj:5 vd:5
+xvssrlrn_bu_h LASX 0111 01010000 10001 vk:5 vj:5 vd:5
+xvssrlrn_hu_w LASX 0111 01010000 10010 vk:5 vj:5 vd:5
+xvssrlrn_wu_d LASX 0111 01010000 10011 vk:5 vj:5 vd:5
+xvssrarn_bu_h LASX 0111 01010000 10101 vk:5 vj:5 vd:5
+xvssrarn_hu_w LASX 0111 01010000 10110 vk:5 vj:5 vd:5
+xvssrarn_wu_d LASX 0111 01010000 10111 vk:5 vj:5 vd:5
+
+xvssrlrni_b_h LASX 0111 01110101 00000 1 imm:4 vj:5 vd:5
+xvssrlrni_h_w LASX 0111 01110101 00001 imm:5 vj:5 vd:5
+xvssrlrni_w_d LASX 0111 01110101 0001 imm:6 vj:5 vd:5
+xvssrlrni_d_q LASX 0111 01110101 001 imm:7 vj:5 vd:5
+xvssrarni_b_h LASX 0111 01110110 10000 1 imm:4 vj:5 vd:5
+xvssrarni_h_w LASX 0111 01110110 10001 imm:5 vj:5 vd:5
+xvssrarni_w_d LASX 0111 01110110 1001 imm:6 vj:5 vd:5
+xvssrarni_d_q LASX 0111 01110110 101 imm:7 vj:5 vd:5
+xvssrlrni_bu_h LASX 0111 01110101 01000 1 imm:4 vj:5 vd:5
+xvssrlrni_hu_w LASX 0111 01110101 01001 imm:5 vj:5 vd:5
+xvssrlrni_wu_d LASX 0111 01110101 0101 imm:6 vj:5 vd:5
+xvssrlrni_du_q LASX 0111 01110101 011 imm:7 vj:5 vd:5
+xvssrarni_bu_h LASX 0111 01110110 11000 1 imm:4 vj:5 vd:5
+xvssrarni_hu_w LASX 0111 01110110 11001 imm:5 vj:5 vd:5
+xvssrarni_wu_d LASX 0111 01110110 1101 imm:6 vj:5 vd:5
+xvssrarni_du_q LASX 0111 01110110 111 imm:7 vj:5 vd:5
+
+xvclo_b LASX 0111 01101001 11000 00000 vj:5 vd:5
+xvclo_h LASX 0111 01101001 11000 00001 vj:5 vd:5
+xvclo_w LASX 0111 01101001 11000 00010 vj:5 vd:5
+xvclo_d LASX 0111 01101001 11000 00011 vj:5 vd:5
+xvclz_b LASX 0111 01101001 11000 00100 vj:5 vd:5
+xvclz_h LASX 0111 01101001 11000 00101 vj:5 vd:5
+xvclz_w LASX 0111 01101001 11000 00110 vj:5 vd:5
+xvclz_d LASX 0111 01101001 11000 00111 vj:5 vd:5
+
+xvpcnt_b LASX 0111 01101001 11000 01000 vj:5 vd:5
+xvpcnt_h LASX 0111 01101001 11000 01001 vj:5 vd:5
+xvpcnt_w LASX 0111 01101001 11000 01010 vj:5 vd:5
+xvpcnt_d LASX 0111 01101001 11000 01011 vj:5 vd:5
+
+xvbitclr_b LASX 0111 01010000 11000 vk:5 vj:5 vd:5
+xvbitclr_h LASX 0111 01010000 11001 vk:5 vj:5 vd:5
+xvbitclr_w LASX 0111 01010000 11010 vk:5 vj:5 vd:5
+xvbitclr_d LASX 0111 01010000 11011 vk:5 vj:5 vd:5
+xvbitclri_b LASX 0111 01110001 00000 01 imm:3 vj:5 vd:5
+xvbitclri_h LASX 0111 01110001 00000 1 imm:4 vj:5 vd:5
+xvbitclri_w LASX 0111 01110001 00001 imm:5 vj:5 vd:5
+xvbitclri_d LASX 0111 01110001 0001 imm:6 vj:5 vd:5
+
+xvbitset_b LASX 0111 01010000 11100 vk:5 vj:5 vd:5
+xvbitset_h LASX 0111 01010000 11101 vk:5 vj:5 vd:5
+xvbitset_w LASX 0111 01010000 11110 vk:5 vj:5 vd:5
+xvbitset_d LASX 0111 01010000 11111 vk:5 vj:5 vd:5
+xvbitseti_b LASX 0111 01110001 01000 01 imm:3 vj:5 vd:5
+xvbitseti_h LASX 0111 01110001 01000 1 imm:4 vj:5 vd:5
+xvbitseti_w LASX 0111 01110001 01001 imm:5 vj:5 vd:5
+xvbitseti_d LASX 0111 01110001 0101 imm:6 vj:5 vd:5
+
+xvbitrev_b LASX 0111 01010001 00000 vk:5 vj:5 vd:5
+xvbitrev_h LASX 0111 01010001 00001 vk:5 vj:5 vd:5
+xvbitrev_w LASX 0111 01010001 00010 vk:5 vj:5 vd:5
+xvbitrev_d LASX 0111 01010001 00011 vk:5 vj:5 vd:5
+xvbitrevi_b LASX 0111 01110001 10000 01 imm:3 vj:5 vd:5
+xvbitrevi_h LASX 0111 01110001 10000 1 imm:4 vj:5 vd:5
+xvbitrevi_w LASX 0111 01110001 10001 imm:5 vj:5 vd:5
+xvbitrevi_d LASX 0111 01110001 1001 imm:6 vj:5 vd:5
+
+xvfrstp_b LASX 0111 01010010 10110 vk:5 vj:5 vd:5
+xvfrstp_h LASX 0111 01010010 10111 vk:5 vj:5 vd:5
+xvfrstpi_b LASX 0111 01101001 10100 imm:5 vj:5 vd:5
+xvfrstpi_h LASX 0111 01101001 10101 imm:5 vj:5 vd:5
+
+xvfadd_s LASX 0111 01010011 00001 vk:5 vj:5 vd:5
+xvfadd_d LASX 0111 01010011 00010 vk:5 vj:5 vd:5
+xvfsub_s LASX 0111 01010011 00101 vk:5 vj:5 vd:5
+xvfsub_d LASX 0111 01010011 00110 vk:5 vj:5 vd:5
+xvfmul_s LASX 0111 01010011 10001 vk:5 vj:5 vd:5
+xvfmul_d LASX 0111 01010011 10010 vk:5 vj:5 vd:5
+xvfdiv_s LASX 0111 01010011 10101 vk:5 vj:5 vd:5
+xvfdiv_d LASX 0111 01010011 10110 vk:5 vj:5 vd:5
+
+xvfmadd_s LASX 0000 10100001 xa:5 vk:5 vj:5 vd:5
+xvfmadd_d LASX 0000 10100010 xa:5 vk:5 vj:5 vd:5
+xvfmsub_s LASX 0000 10100101 xa:5 vk:5 vj:5 vd:5
+xvfmsub_d LASX 0000 10100110 xa:5 vk:5 vj:5 vd:5
+xvfnmadd_s LASX 0000 10101001 xa:5 vk:5 vj:5 vd:5
+xvfnmadd_d LASX 0000 10101010 xa:5 vk:5 vj:5 vd:5
+xvfnmsub_s LASX 0000 10101101 xa:5 vk:5 vj:5 vd:5
+xvfnmsub_d LASX 0000 10101110 xa:5 vk:5 vj:5 vd:5
+
+xvfmax_s LASX 0111 01010011 11001 vk:5 vj:5 vd:5
+xvfmax_d LASX 0111 01010011 11010 vk:5 vj:5 vd:5
+xvfmin_s LASX 0111 01010011 11101 vk:5 vj:5 vd:5
+xvfmin_d LASX 0111 01010011 11110 vk:5 vj:5 vd:5
+
+xvfmaxa_s LASX 0111 01010100 00001 vk:5 vj:5 vd:5
+xvfmaxa_d LASX 0111 01010100 00010 vk:5 vj:5 vd:5
+xvfmina_s LASX 0111 01010100 00101 vk:5 vj:5 vd:5
+xvfmina_d LASX 0111 01010100 00110 vk:5 vj:5 vd:5
+
+xvflogb_s LASX 0111 01101001 11001 10001 vj:5 vd:5
+xvflogb_d LASX 0111 01101001 11001 10010 vj:5 vd:5
+
+xvfclass_s LASX 0111 01101001 11001 10101 vj:5 vd:5
+xvfclass_d LASX 0111 01101001 11001 10110 vj:5 vd:5
+
+xvfsqrt_s LASX 0111 01101001 11001 11001 vj:5 vd:5
+xvfsqrt_d LASX 0111 01101001 11001 11010 vj:5 vd:5
+xvfrecip_s LASX 0111 01101001 11001 11101 vj:5 vd:5
+xvfrecip_d LASX 0111 01101001 11001 11110 vj:5 vd:5
+xvfrsqrt_s LASX 0111 01101001 11010 00001 vj:5 vd:5
+xvfrsqrt_d LASX 0111 01101001 11010 00010 vj:5 vd:5
+
+xvfcvtl_s_h LASX 0111 01101001 11011 11010 vj:5 vd:5
+xvfcvth_s_h LASX 0111 01101001 11011 11011 vj:5 vd:5
+xvfcvtl_d_s LASX 0111 01101001 11011 11100 vj:5 vd:5
+xvfcvth_d_s LASX 0111 01101001 11011 11101 vj:5 vd:5
+xvfcvt_h_s LASX 0111 01010100 01100 vk:5 vj:5 vd:5
+xvfcvt_s_d LASX 0111 01010100 01101 vk:5 vj:5 vd:5
+
+xvfrintrne_s LASX 0111 01101001 11010 11101 vj:5 vd:5
+xvfrintrne_d LASX 0111 01101001 11010 11110 vj:5 vd:5
+xvfrintrz_s LASX 0111 01101001 11010 11001 vj:5 vd:5
+xvfrintrz_d LASX 0111 01101001 11010 11010 vj:5 vd:5
+xvfrintrp_s LASX 0111 01101001 11010 10101 vj:5 vd:5
+xvfrintrp_d LASX 0111 01101001 11010 10110 vj:5 vd:5
+xvfrintrm_s LASX 0111 01101001 11010 10001 vj:5 vd:5
+xvfrintrm_d LASX 0111 01101001 11010 10010 vj:5 vd:5
+xvfrint_s LASX 0111 01101001 11010 01101 vj:5 vd:5
+xvfrint_d LASX 0111 01101001 11010 01110 vj:5 vd:5
+
+xvftintrne_w_s LASX 0111 01101001 11100 10100 vj:5 vd:5
+xvftintrne_l_d LASX 0111 01101001 11100 10101 vj:5 vd:5
+xvftintrz_w_s LASX 0111 01101001 11100 10010 vj:5 vd:5
+xvftintrz_l_d LASX 0111 01101001 11100 10011 vj:5 vd:5
+xvftintrp_w_s LASX 0111 01101001 11100 10000 vj:5 vd:5
+xvftintrp_l_d LASX 0111 01101001 11100 10001 vj:5 vd:5
+xvftintrm_w_s LASX 0111 01101001 11100 01110 vj:5 vd:5
+xvftintrm_l_d LASX 0111 01101001 11100 01111 vj:5 vd:5
+xvftint_w_s LASX 0111 01101001 11100 01100 vj:5 vd:5
+xvftint_l_d LASX 0111 01101001 11100 01101 vj:5 vd:5
+xvftintrz_wu_s LASX 0111 01101001 11100 11100 vj:5 vd:5
+xvftintrz_lu_d LASX 0111 01101001 11100 11101 vj:5 vd:5
+xvftint_wu_s LASX 0111 01101001 11100 10110 vj:5 vd:5
+xvftint_lu_d LASX 0111 01101001 11100 10111 vj:5 vd:5
+
+xvftintrne_w_d LASX 0111 01010100 10111 vk:5 vj:5 vd:5
+xvftintrz_w_d LASX 0111 01010100 10110 vk:5 vj:5 vd:5
+xvftintrp_w_d LASX 0111 01010100 10101 vk:5 vj:5 vd:5
+xvftintrm_w_d LASX 0111 01010100 10100 vk:5 vj:5 vd:5
+xvftint_w_d LASX 0111 01010100 10011 vk:5 vj:5 vd:5
+
+xvftintrnel_l_s LASX 0111 01101001 11101 01000 vj:5 vd:5
+xvftintrneh_l_s LASX 0111 01101001 11101 01001 vj:5 vd:5
+xvftintrzl_l_s LASX 0111 01101001 11101 00110 vj:5 vd:5
+xvftintrzh_l_s LASX 0111 01101001 11101 00111 vj:5 vd:5
+xvftintrpl_l_s LASX 0111 01101001 11101 00100 vj:5 vd:5
+xvftintrph_l_s LASX 0111 01101001 11101 00101 vj:5 vd:5
+xvftintrml_l_s LASX 0111 01101001 11101 00010 vj:5 vd:5
+xvftintrmh_l_s LASX 0111 01101001 11101 00011 vj:5 vd:5
+xvftintl_l_s LASX 0111 01101001 11101 00000 vj:5 vd:5
+xvftinth_l_s LASX 0111 01101001 11101 00001 vj:5 vd:5
+
+xvffint_s_w LASX 0111 01101001 11100 00000 vj:5 vd:5
+xvffint_d_l LASX 0111 01101001 11100 00010 vj:5 vd:5
+xvffint_s_wu LASX 0111 01101001 11100 00001 vj:5 vd:5
+xvffint_d_lu LASX 0111 01101001 11100 00011 vj:5 vd:5
+xvffintl_d_w LASX 0111 01101001 11100 00100 vj:5 vd:5
+xvffinth_d_w LASX 0111 01101001 11100 00101 vj:5 vd:5
+xvffint_s_l LASX 0111 01010100 10000 vk:5 vj:5 vd:5
+
+xvseq_b LASX 0111 01000000 00000 vk:5 vj:5 vd:5
+xvseq_h LASX 0111 01000000 00001 vk:5 vj:5 vd:5
+xvseq_w LASX 0111 01000000 00010 vk:5 vj:5 vd:5
+xvseq_d LASX 0111 01000000 00011 vk:5 vj:5 vd:5
+xvseqi_b LASX 0111 01101000 00000 si5:5 vj:5 vd:5
+xvseqi_h LASX 0111 01101000 00001 si5:5 vj:5 vd:5
+xvseqi_w LASX 0111 01101000 00010 si5:5 vj:5 vd:5
+xvseqi_d LASX 0111 01101000 00011 si5:5 vj:5 vd:5
+
+xvsle_b LASX 0111 01000000 00100 vk:5 vj:5 vd:5
+xvsle_h LASX 0111 01000000 00101 vk:5 vj:5 vd:5
+xvsle_w LASX 0111 01000000 00110 vk:5 vj:5 vd:5
+xvsle_d LASX 0111 01000000 00111 vk:5 vj:5 vd:5
+xvslei_b LASX 0111 01101000 00100 si5:5 vj:5 vd:5
+xvslei_h LASX 0111 01101000 00101 si5:5 vj:5 vd:5
+xvslei_w LASX 0111 01101000 00110 si5:5 vj:5 vd:5
+xvslei_d LASX 0111 01101000 00111 si5:5 vj:5 vd:5
+xvsle_bu LASX 0111 01000000 01000 vk:5 vj:5 vd:5
+xvsle_hu LASX 0111 01000000 01001 vk:5 vj:5 vd:5
+xvsle_wu LASX 0111 01000000 01010 vk:5 vj:5 vd:5
+xvsle_du LASX 0111 01000000 01011 vk:5 vj:5 vd:5
+xvslei_bu LASX 0111 01101000 01000 imm:5 vj:5 vd:5
+xvslei_hu LASX 0111 01101000 01001 imm:5 vj:5 vd:5
+xvslei_wu LASX 0111 01101000 01010 imm:5 vj:5 vd:5
+xvslei_du LASX 0111 01101000 01011 imm:5 vj:5 vd:5
+
+xvslt_b LASX 0111 01000000 01100 vk:5 vj:5 vd:5
+xvslt_h LASX 0111 01000000 01101 vk:5 vj:5 vd:5
+xvslt_w LASX 0111 01000000 01110 vk:5 vj:5 vd:5
+xvslt_d LASX 0111 01000000 01111 vk:5 vj:5 vd:5
+xvslti_b LASX 0111 01101000 01100 si5:5 vj:5 vd:5
+xvslti_h LASX 0111 01101000 01101 si5:5 vj:5 vd:5
+xvslti_w LASX 0111 01101000 01110 si5:5 vj:5 vd:5
+xvslti_d LASX 0111 01101000 01111 si5:5 vj:5 vd:5
+xvslt_bu LASX 0111 01000000 10000 vk:5 vj:5 vd:5
+xvslt_hu LASX 0111 01000000 10001 vk:5 vj:5 vd:5
+xvslt_wu LASX 0111 01000000 10010 vk:5 vj:5 vd:5
+xvslt_du LASX 0111 01000000 10011 vk:5 vj:5 vd:5
+xvslti_bu LASX 0111 01101000 10000 imm:5 vj:5 vd:5
+xvslti_hu LASX 0111 01101000 10001 imm:5 vj:5 vd:5
+xvslti_wu LASX 0111 01101000 10010 imm:5 vj:5 vd:5
+xvslti_du LASX 0111 01101000 10011 imm:5 vj:5 vd:5
+
+xvfcmp_cond_s LASX 0000 11001001 cond:5 vk:5 vj:5 vd:5 \
+ !constraints { $cond > 0 && $cond < 0x12; }
+xvfcmp_cond_d LASX 0000 11001010 cond:5 vk:5 vj:5 vd:5 \
+ !constraints { $cond > 0 && $cond < 0x12; }
+
+xvbitsel_v LASX 0000 11010010 xa:5 vk:5 vj:5 vd:5
+xvbitseli_b LASX 0111 01111100 01 imm:8 vj:5 vd:5
+
+xvseteqz_v LASX 0111 01101001 11001 00110 vj:5 00 cd:3
+xvsetnez_v LASX 0111 01101001 11001 00111 vj:5 00 cd:3
+xvsetanyeqz_b LASX 0111 01101001 11001 01000 vj:5 00 cd:3
+xvsetanyeqz_h LASX 0111 01101001 11001 01001 vj:5 00 cd:3
+xvsetanyeqz_w LASX 0111 01101001 11001 01010 vj:5 00 cd:3
+xvsetanyeqz_d LASX 0111 01101001 11001 01011 vj:5 00 cd:3
+xvsetallnez_b LASX 0111 01101001 11001 01100 vj:5 00 cd:3
+xvsetallnez_h LASX 0111 01101001 11001 01101 vj:5 00 cd:3
+xvsetallnez_w LASX 0111 01101001 11001 01110 vj:5 00 cd:3
+xvsetallnez_d LASX 0111 01101001 11001 01111 vj:5 00 cd:3
+
+xvinsgr2vr_w LASX 0111 01101110 10111 10 imm:3 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+xvinsgr2vr_d LASX 0111 01101110 10111 110 imm:2 rj:5 vd:5 \
+ !constraints { $rj != 2 && $rj != 0; }
+xvpickve2gr_w LASX 0111 01101110 11111 10 imm:3 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+xvpickve2gr_d LASX 0111 01101110 11111 110 imm:2 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+xvpickve2gr_wu LASX 0111 01101111 00111 10 imm:3 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+xvpickve2gr_du LASX 0111 01101111 00111 110 imm:2 vj:5 rd:5 \
+ !constraints { $rd != 2 && $rd != 0; }
+
+xvrepl128vei_b LASX 0111 01101111 01111 0 imm:4 vj:5 vd:5
+xvrepl128vei_h LASX 0111 01101111 01111 10 imm:3 vj:5 vd:5
+xvrepl128vei_w LASX 0111 01101111 01111 110 imm:2 vj:5 vd:5
+xvrepl128vei_d LASX 0111 01101111 01111 1110 imm:1 vj:5 vd:5
+
+xvreplve_b LASX 0111 01010010 00100 rk:5 vj:5 vd:5
+xvreplve_h LASX 0111 01010010 00101 rk:5 vj:5 vd:5
+xvreplve_w LASX 0111 01010010 00110 rk:5 vj:5 vd:5
+xvreplve_d LASX 0111 01010010 00111 rk:5 vj:5 vd:5
+
+xvreplve0_b LASX 0111 01110000 01110 00000 vj:5 vd:5
+xvreplve0_h LASX 0111 01110000 01111 00000 vj:5 vd:5
+xvreplve0_w LASX 0111 01110000 01111 10000 vj:5 vd:5
+xvreplve0_d LASX 0111 01110000 01111 11000 vj:5 vd:5
+xvreplve0_q LASX 0111 01110000 01111 11100 vj:5 vd:5
+
+xvinsve0_w LASX 0111 01101111 11111 10 imm:3 vj:5 vd:5
+xvinsve0_d LASX 0111 01101111 11111 110 imm:2 vj:5 vd:5
+
+xvpickve_w LASX 0111 01110000 00111 10 imm:3 vj:5 vd:5
+xvpickve_d LASX 0111 01110000 00111 110 imm:2 vj:5 vd:5
+
+xvbsll_v LASX 0111 01101000 11100 imm:5 vj:5 vd:5
+xvbsrl_v LASX 0111 01101000 11101 imm:5 vj:5 vd:5
+
+xvpackev_b LASX 0111 01010001 01100 vk:5 vj:5 vd:5
+xvpackev_h LASX 0111 01010001 01101 vk:5 vj:5 vd:5
+xvpackev_w LASX 0111 01010001 01110 vk:5 vj:5 vd:5
+xvpackev_d LASX 0111 01010001 01111 vk:5 vj:5 vd:5
+xvpackod_b LASX 0111 01010001 10000 vk:5 vj:5 vd:5
+xvpackod_h LASX 0111 01010001 10001 vk:5 vj:5 vd:5
+xvpackod_w LASX 0111 01010001 10010 vk:5 vj:5 vd:5
+xvpackod_d LASX 0111 01010001 10011 vk:5 vj:5 vd:5
+
+xvpickev_b LASX 0111 01010001 11100 vk:5 vj:5 vd:5
+xvpickev_h LASX 0111 01010001 11101 vk:5 vj:5 vd:5
+xvpickev_w LASX 0111 01010001 11110 vk:5 vj:5 vd:5
+xvpickev_d LASX 0111 01010001 11111 vk:5 vj:5 vd:5
+xvpickod_b LASX 0111 01010010 00000 vk:5 vj:5 vd:5
+xvpickod_h LASX 0111 01010010 00001 vk:5 vj:5 vd:5
+xvpickod_w LASX 0111 01010010 00010 vk:5 vj:5 vd:5
+xvpickod_d LASX 0111 01010010 00011 vk:5 vj:5 vd:5
+
+xvilvl_b LASX 0111 01010001 10100 vk:5 vj:5 vd:5
+xvilvl_h LASX 0111 01010001 10101 vk:5 vj:5 vd:5
+xvilvl_w LASX 0111 01010001 10110 vk:5 vj:5 vd:5
+xvilvl_d LASX 0111 01010001 10111 vk:5 vj:5 vd:5
+xvilvh_b LASX 0111 01010001 11000 vk:5 vj:5 vd:5
+xvilvh_h LASX 0111 01010001 11001 vk:5 vj:5 vd:5
+xvilvh_w LASX 0111 01010001 11010 vk:5 vj:5 vd:5
+xvilvh_d LASX 0111 01010001 11011 vk:5 vj:5 vd:5
+
+#xvshuf_b LASX 0000 11010110 xa:5 vk:5 vj:5 vd:5
+#xvshuf_h LASX 0111 01010111 10101 vk:5 vj:5 vd:5
+#xvshuf_w LASX 0111 01010111 10110 vk:5 vj:5 vd:5
+#xvshuf_d LASX 0111 01010111 10111 vk:5 vj:5 vd:5
+
+xvperm_w LASX 0111 01010111 11010 vk:5 vj:5 vd:5
+
+xvshuf4i_b LASX 0111 01111001 00 imm:8 vj:5 vd:5
+xvshuf4i_h LASX 0111 01111001 01 imm:8 vj:5 vd:5
+xvshuf4i_w LASX 0111 01111001 10 imm:8 vj:5 vd:5
+xvshuf4i_d LASX 0111 01111001 11 imm:8 vj:5 vd:5
+
+xvpermi_w LASX 0111 01111110 01 imm:8 vj:5 vd:5
+xvpermi_d LASX 0111 01111110 10 imm:8 vj:5 vd:5
+#xvpermi_q LASX 0111 01111110 11 imm:8 vj:5 vd:5
+
+xvextrins_d LASX 0111 01111000 00 imm:8 vj:5 vd:5
+xvextrins_w LASX 0111 01111000 01 imm:8 vj:5 vd:5
+xvextrins_h LASX 0111 01111000 10 imm:8 vj:5 vd:5
+xvextrins_b LASX 0111 01111000 11 imm:8 vj:5 vd:5
+
+xvld LASX 0010 110010 si12:12 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+xvst LASX 0010 110011 si12:12 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+xvldx LASX 0011 10000100 10000 rk:5 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != $rk && $rk != 2 && $rj != 2; } \
+ !memory { reg_plus_reg($rj, $rk); }
+xvstx LASX 0011 10000100 11000 rk:5 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != $rk && $rk != 2 && $rj != 2; } \
+ !memory { reg_plus_reg($rj, $rk); }
+
+xvldrepl_d LASX 0011 00100001 0 si9:9 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si9, 9) * 8); }
+xvldrepl_w LASX 0011 00100010 si10:10 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si10, 10) * 4); }
+xvldrepl_h LASX 0011 0010010 si11:11 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si11, 11) * 2); }
+xvldrepl_b LASX 0011 001010 si12:12 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+
+xvstelm_d LASX 0011 00110001 si2:2 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 8); }
+xvstelm_w LASX 0011 0011001 si3:3 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 4); }
+xvstelm_h LASX 0011 001101 si4:4 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 2); }
+xvstelm_b LASX 0011 00111 si5:5 si8:8 rj:5 vd:5 \
+ !constraints { $rj != 0 && $rj != 2; } \
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 2); }
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [risu PATCH 3/5] loongarch: reginfo suport LSX/LASX
2023-10-25 9:29 [risu PATCH 0/5] Add LoongArch LSX/LASX instructions Song Gao
2023-10-25 9:29 ` [risu PATCH 1/5] loongarch: Add LSX instructions Song Gao
2023-10-25 9:29 ` [risu PATCH 2/5] loongarch: Add LASX instructions Song Gao
@ 2023-10-25 9:29 ` Song Gao
2023-10-25 9:29 ` [risu PATCH 4/5] loongarch: init LASX registers Song Gao
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Song Gao @ 2023-10-25 9:29 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
risu_reginfo_loongarch64.c | 107 +++++++++++++++++++++++++++++++++----
risu_reginfo_loongarch64.h | 3 +-
2 files changed, 98 insertions(+), 12 deletions(-)
diff --git a/risu_reginfo_loongarch64.c b/risu_reginfo_loongarch64.c
index 16384f1..09a1eb6 100644
--- a/risu_reginfo_loongarch64.c
+++ b/risu_reginfo_loongarch64.c
@@ -37,6 +37,8 @@ struct extctx_layout {
unsigned long size;
unsigned int flags;
struct _ctx_layout fpu;
+ struct _ctx_layout lsx;
+ struct _ctx_layout lasx;
struct _ctx_layout end;
};
@@ -72,6 +74,20 @@ static int parse_extcontext(struct sigcontext *sc, struct extctx_layout *extctx)
}
extctx->fpu.addr = info;
break;
+ case LSX_CTX_MAGIC:
+ if (size < (sizeof(struct sctx_info) +
+ sizeof(struct lsx_context))) {
+ return -1;
+ }
+ extctx->lsx.addr = info;
+ break;
+ case LASX_CTX_MAGIC:
+ if (size < (sizeof(struct sctx_info) +
+ sizeof(struct lasx_context))) {
+ return -1;
+ }
+ extctx->lasx.addr = info;
+ break;
default:
return -1;
}
@@ -100,15 +116,40 @@ void reginfo_init(struct reginfo *ri, ucontext_t *context, void *siaddr)
ri->faulting_insn = *(uint32_t *)uc->uc_mcontext.sc_pc;
parse_extcontext(&uc->uc_mcontext, &extctx);
- if (extctx.fpu.addr) {
+ if (extctx.lasx.addr) {
+ struct sctx_info *info = extctx.lasx.addr;
+ struct lasx_context *lasx_ctx = (struct lasx_context *)((char *)info +
+ sizeof(struct sctx_info));
+ for (i = 0; i < 32; i++) {
+ ri->vregs[4 * i] = lasx_ctx->regs[4 * i];
+ ri->vregs[4 * i + 1] = lasx_ctx->regs[4 * i + 1];
+ ri->vregs[4 * i + 2] = lasx_ctx->regs[4 * i + 2];
+ ri->vregs[4 * i + 3] = lasx_ctx->regs[4 * i + 3];
+ }
+ ri->fcsr = lasx_ctx->fcsr;
+ ri->fcc = lasx_ctx->fcc;
+ ri->vl = 256;
+ } else if (extctx.lsx.addr) {
+ struct sctx_info *info = extctx.lsx.addr;
+ struct lsx_context *lsx_ctx = (struct lsx_context *)((char *)info +
+ sizeof(struct sctx_info));
+ for (i = 0; i < 32; i++) {
+ ri->vregs[4 * i] = lsx_ctx->regs[4 * i + 1];
+ ri->vregs[4 * i + 1] = lsx_ctx->regs[4 * i + 1];
+ }
+ ri->fcsr = lsx_ctx->fcsr;
+ ri->fcc = lsx_ctx->fcc;
+ ri->vl = 128;
+ } else if (extctx.fpu.addr) {
struct sctx_info *info = extctx.fpu.addr;
struct fpu_context *fpu_ctx = (struct fpu_context *)((char *)info +
- sizeof(struct sctx_info));
+ sizeof(struct sctx_info));
for(i = 0; i < 32; i++) {
- ri->fpregs[i] = fpu_ctx->regs[i];
+ ri->vregs[4 * i] = fpu_ctx->regs[4 * i];
}
- ri->fcsr = fpu_ctx->fcsr;
- ri->fcc = fpu_ctx->fcc;
+ ri->fcsr = fpu_ctx->fcsr;
+ ri->fcc = fpu_ctx->fcc;
+ ri->vl = 64;
}
}
@@ -132,9 +173,23 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
fprintf(f, " flags : %08x\n", ri->flags);
fprintf(f, " fcc : %016" PRIx64 "\n", ri->fcc);
fprintf(f, " fcsr : %08x\n", ri->fcsr);
+ fprintf(f, " vl : %016" PRIx64 "\n", ri->vl);
- for (i = 0; i < 32; i++) {
- fprintf(f, " f%-2d : %016lx\n", i, ri->fpregs[i]);
+ if (ri->vl == 256) {
+ for (i = 0; i < 32; i++) {
+ fprintf(f, " vreg%-2d : {%016lx, %016lx, %016lx, %016lx}\n", i,
+ ri->vregs[4 * i + 3], ri->vregs[4 * i + 2],
+ ri->vregs[4 * i + 1], ri->vregs[4 * i]);
+ }
+ } else if (ri->vl == 128) {
+ for (i = 0; i < 32; i++) {
+ fprintf(f, " vreg%-2d : {%016lx, %016lx}\n", i,
+ ri->vregs[4 * i + 1], ri->vregs[4 * i]);
+ }
+ } else if (ri->vl == 64) {
+ for (i = 0; i < 32; i++) {
+ fprintf(f, " vreg%-2d : %016lx\n", i, ri->vregs[4 * i]);
+ }
}
return !ferror(f);
@@ -145,6 +200,11 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
{
int i;
fprintf(f, "mismatch detail (master : apprentice):\n");
+
+ if (m->vl != a->vl) {
+ fprintf(f, " vl mismatch %08lx vs %08lx\n", m->vl, a->vl);
+ }
+
if (m->faulting_insn != a->faulting_insn) {
fprintf(f, " faulting insn mismatch %08x vs %08x\n",
m->faulting_insn, a->faulting_insn);
@@ -172,10 +232,35 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr);
}
- for (i = 0; i < 32; i++) {
- if (m->fpregs[i]!= a->fpregs[i]) {
- fprintf(f, " f%-2d : %016lx vs %016lx\n",
- i, m->fpregs[i], a->fpregs[i]);
+ if (m->vl == 256) {
+ for (i = 0; i < 32; i++) {
+ if (m->vregs[4 * i + 3] != a->vregs[4 * i + 3] ||
+ m->vregs[4 * i + 2] != a->vregs[4 * i + 2] ||
+ m->vregs[4 * i + 1] != a->vregs[4 * i + 1] ||
+ m->vregs[4 * i] != a->vregs[4 * i]) {
+ fprintf(f, " vreg%-2d : {%016lx, %016lx, %016lx, %016lx} vs"
+ " {%016lx, %016lx, %016lx, %016lx}\n", i,
+ m->vregs[4 * i + 3], m->vregs[4 * i + 2],
+ m->vregs[4 * i + 1], m->vregs[4 * i],
+ a->vregs[4 * i + 3], a->vregs[4 * i + 2],
+ a->vregs[4 * i + 1], a->vregs[4 * i]);
+ }
+ }
+ } else if (m->vl == 128) {
+ for (i = 0; i < 32; i++) {
+ if (m->vregs[4 * i + 1] != a->vregs[4 * i + 1] ||
+ m->vregs[4 * i] != a->vregs[4 * i]) {
+ fprintf(f, " vreg%-2d : {%016lx, %016lx} vs {%016lx, %016lx}\n",
+ i, m->vregs[4 * i + 1], m->vregs[4 * i],
+ a->vregs[4 * i + 1], m->vregs[4 * i]);
+ }
+ }
+ } else if (m->vl == 64) {
+ for (i = 0; i < 32; i++) {
+ if (m->vregs[4 * i] != a->vregs[4 * i]) {
+ fprintf(f, " vreg%-2d : %016lx vs %016lx\n", i,
+ m->vregs[4 * i], a->vregs[4 * i]);
+ }
}
}
diff --git a/risu_reginfo_loongarch64.h b/risu_reginfo_loongarch64.h
index b6c5aaa..892b477 100644
--- a/risu_reginfo_loongarch64.h
+++ b/risu_reginfo_loongarch64.h
@@ -19,7 +19,8 @@ struct reginfo {
uint32_t flags;
uint32_t fcsr;
uint32_t faulting_insn;
- uint64_t fpregs[32];
+ uint64_t vregs[4 * 32];
+ uint64_t vl;
};
#endif /* RISU_REGINFO_LOONGARCH64_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [risu PATCH 4/5] loongarch: init LASX registers
2023-10-25 9:29 [risu PATCH 0/5] Add LoongArch LSX/LASX instructions Song Gao
` (2 preceding siblings ...)
2023-10-25 9:29 ` [risu PATCH 3/5] loongarch: reginfo suport LSX/LASX Song Gao
@ 2023-10-25 9:29 ` Song Gao
2023-10-25 9:29 ` [risu PATCH 5/5] loongarch: Add block 'clean' and clean_lsx_result() Song Gao
2023-11-13 8:06 ` [risu PATCH 0/5] Add LoongArch LSX/LASX instructions gaosong
5 siblings, 0 replies; 11+ messages in thread
From: Song Gao @ 2023-10-25 9:29 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
Most of LoongArch cpus have LSX and LASX, so we can init LASX registers
for risu test. We use $f0-$f31 value to init LASX $vreg0- $vreg31 registers.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
risugen_loongarch64.pm | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/risugen_loongarch64.pm b/risugen_loongarch64.pm
index 5394fdc..b3f901d 100644
--- a/risugen_loongarch64.pm
+++ b/risugen_loongarch64.pm
@@ -374,6 +374,16 @@ sub write_random_register_data($)
if ($fp_enabled) {
# Load floating point registers
write_random_loongarch64_fpdata();
+
+ # Write random LASX data.
+ for (my $i = 0; $i < 32; $i++) {
+ my $tmp_reg = 6;
+ # $fi is lasx register initial value.
+ # movfr2gr.d r6 fi
+ insn32(0x114b800 | $i << 5 | $tmp_reg);
+ # xvreplgr2vr_d $i r6
+ insn32(0x769f0c00 | 6 << 5 | $i);
+ }
}
write_random_regdata();
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [risu PATCH 5/5] loongarch: Add block 'clean' and clean_lsx_result()
2023-10-25 9:29 [risu PATCH 0/5] Add LoongArch LSX/LASX instructions Song Gao
` (3 preceding siblings ...)
2023-10-25 9:29 ` [risu PATCH 4/5] loongarch: init LASX registers Song Gao
@ 2023-10-25 9:29 ` Song Gao
2023-12-12 12:39 ` Peter Maydell
2023-11-13 8:06 ` [risu PATCH 0/5] Add LoongArch LSX/LASX instructions gaosong
5 siblings, 1 reply; 11+ messages in thread
From: Song Gao @ 2023-10-25 9:29 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
The result of the LSX instruction is in the low 128 bits
of the vreg register. We use clean_lsx_result() to clean up
the high 128 bits of the vreg register.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
loongarch64.risu | 2121 ++++++++++++++++++++++++++--------------
risugen | 2 +-
risugen_loongarch64.pm | 20 +
3 files changed, 1405 insertions(+), 738 deletions(-)
diff --git a/loongarch64.risu b/loongarch64.risu
index 596de90..531470d 100644
--- a/loongarch64.risu
+++ b/loongarch64.risu
@@ -64,26 +64,26 @@ mulw_d_wu LA64 0000 00000001 11111 rk:5 rj:5 rd:5 \
#div.{w[u]/d[u]} rd,rj,rk
# div.w{u}, mod.w[u] rk, rj, need in [0x0 ~0x7FFFFFFF]
# use function set_reg_w($reg)
-div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
- !memory { set_reg_w($rj); set_reg_w($rk); }
-div_wu LA64 0000 00000010 00010 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
- !memory { set_reg_w($rj); set_reg_w($rk); }
-div_d LA64 0000 00000010 00100 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
-div_du LA64 0000 00000010 00110 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
-mod_w LA64 0000 00000010 00001 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
- !memory { set_reg_w($rj); set_reg_w($rk); }
-mod_wu LA64 0000 00000010 00011 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
- !memory { set_reg_w($rj); set_reg_w($rk); }
-mod_d LA64 0000 00000010 00101 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
-mod_du LA64 0000 00000010 00111 rk:5 rj:5 rd:5 \
- !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
+#div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
+# !memory { set_reg_w($rj); set_reg_w($rk); }
+#div_wu LA64 0000 00000010 00010 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
+# !memory { set_reg_w($rj); set_reg_w($rk); }
+#div_d LA64 0000 00000010 00100 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
+#div_du LA64 0000 00000010 00110 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
+#mod_w LA64 0000 00000010 00001 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
+# !memory { set_reg_w($rj); set_reg_w($rk); }
+#mod_wu LA64 0000 00000010 00011 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
+# !memory { set_reg_w($rj); set_reg_w($rk); }
+#mod_d LA64 0000 00000010 00101 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
+#mod_du LA64 0000 00000010 00111 rk:5 rj:5 rd:5 \
+# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
alsl_w LA64 0000 00000000 010 sa2:2 rk:5 rj:5 rd:5 \
!constraints { $rk != 2 && $rj != 2 && $rd != 2; }
@@ -615,665 +615,1248 @@ fstx_d LA64 0011 10000011 11000 rk:5 rj:5 fd:5 \
# LSX instructions
#
-vadd_b LSX 0111 00000000 10100 vk:5 vj:5 vd:5
-vadd_h LSX 0111 00000000 10101 vk:5 vj:5 vd:5
-vadd_w LSX 0111 00000000 10110 vk:5 vj:5 vd:5
-vadd_d LSX 0111 00000000 10111 vk:5 vj:5 vd:5
-vadd_q LSX 0111 00010010 11010 vk:5 vj:5 vd:5
-vsub_b LSX 0111 00000000 11000 vk:5 vj:5 vd:5
-vsub_h LSX 0111 00000000 11001 vk:5 vj:5 vd:5
-vsub_w LSX 0111 00000000 11010 vk:5 vj:5 vd:5
-vsub_d LSX 0111 00000000 11011 vk:5 vj:5 vd:5
-vsub_q LSX 0111 00010010 11011 vk:5 vj:5 vd:5
-
-vaddi_bu LSX 0111 00101000 10100 imm:5 vj:5 vd:5
-vaddi_hu LSX 0111 00101000 10101 imm:5 vj:5 vd:5
-vaddi_wu LSX 0111 00101000 10110 imm:5 vj:5 vd:5
-vaddi_du LSX 0111 00101000 10111 imm:5 vj:5 vd:5
-vsubi_bu LSX 0111 00101000 11000 imm:5 vj:5 vd:5
-vsubi_hu LSX 0111 00101000 11001 imm:5 vj:5 vd:5
-vsubi_wu LSX 0111 00101000 11010 imm:5 vj:5 vd:5
-vsubi_du LSX 0111 00101000 11011 imm:5 vj:5 vd:5
-
-vneg_b LSX 0111 00101001 11000 01100 vj:5 vd:5
-vneg_h LSX 0111 00101001 11000 01101 vj:5 vd:5
-vneg_w LSX 0111 00101001 11000 01110 vj:5 vd:5
-vneg_d LSX 0111 00101001 11000 01111 vj:5 vd:5
-
-vsadd_b LSX 0111 00000100 01100 vk:5 vj:5 vd:5
-vsadd_h LSX 0111 00000100 01101 vk:5 vj:5 vd:5
-vsadd_w LSX 0111 00000100 01110 vk:5 vj:5 vd:5
-vsadd_d LSX 0111 00000100 01111 vk:5 vj:5 vd:5
-vsadd_bu LSX 0111 00000100 10100 vk:5 vj:5 vd:5
-vsadd_hu LSX 0111 00000100 10101 vk:5 vj:5 vd:5
-vsadd_wu LSX 0111 00000100 10110 vk:5 vj:5 vd:5
-vsadd_du LSX 0111 00000100 10111 vk:5 vj:5 vd:5
-
-vssub_b LSX 0111 00000100 10000 vk:5 vj:5 vd:5
-vssub_h LSX 0111 00000100 10001 vk:5 vj:5 vd:5
-vssub_w LSX 0111 00000100 10010 vk:5 vj:5 vd:5
-vssub_d LSX 0111 00000100 10011 vk:5 vj:5 vd:5
-vssub_bu LSX 0111 00000100 11000 vk:5 vj:5 vd:5
-vssub_hu LSX 0111 00000100 11001 vk:5 vj:5 vd:5
-vssub_wu LSX 0111 00000100 11010 vk:5 vj:5 vd:5
-vssub_du LSX 0111 00000100 11011 vk:5 vj:5 vd:5
-
-vhaddw_h_b LSX 0111 00000101 01000 vk:5 vj:5 vd:5
-vhaddw_w_h LSX 0111 00000101 01001 vk:5 vj:5 vd:5
-vhaddw_d_w LSX 0111 00000101 01010 vk:5 vj:5 vd:5
-vhaddw_q_d LSX 0111 00000101 01011 vk:5 vj:5 vd:5
-vhaddw_hu_bu LSX 0111 00000101 10000 vk:5 vj:5 vd:5
-vhaddw_wu_hu LSX 0111 00000101 10001 vk:5 vj:5 vd:5
-vhaddw_du_wu LSX 0111 00000101 10010 vk:5 vj:5 vd:5
-vhaddw_qu_du LSX 0111 00000101 10011 vk:5 vj:5 vd:5
-
-vhsubw_h_b LSX 0111 00000101 01100 vk:5 vj:5 vd:5
-vhsubw_w_h LSX 0111 00000101 01101 vk:5 vj:5 vd:5
-vhsubw_d_w LSX 0111 00000101 01110 vk:5 vj:5 vd:5
-vhsubw_q_d LSX 0111 00000101 01111 vk:5 vj:5 vd:5
-vhsubw_hu_bu LSX 0111 00000101 10100 vk:5 vj:5 vd:5
-vhsubw_wu_hu LSX 0111 00000101 10101 vk:5 vj:5 vd:5
-vhsubw_du_wu LSX 0111 00000101 10110 vk:5 vj:5 vd:5
-vhsubw_qu_du LSX 0111 00000101 10111 vk:5 vj:5 vd:5
-
-vaddwev_h_b LSX 0111 00000001 11100 vk:5 vj:5 vd:5
-vaddwev_w_h LSX 0111 00000001 11101 vk:5 vj:5 vd:5
-vaddwev_d_w LSX 0111 00000001 11110 vk:5 vj:5 vd:5
-vaddwev_q_d LSX 0111 00000001 11111 vk:5 vj:5 vd:5
-vaddwod_h_b LSX 0111 00000010 00100 vk:5 vj:5 vd:5
-vaddwod_w_h LSX 0111 00000010 00101 vk:5 vj:5 vd:5
-vaddwod_d_w LSX 0111 00000010 00110 vk:5 vj:5 vd:5
-vaddwod_q_d LSX 0111 00000010 00111 vk:5 vj:5 vd:5
-
-vsubwev_h_b LSX 0111 00000010 00000 vk:5 vj:5 vd:5
-vsubwev_w_h LSX 0111 00000010 00001 vk:5 vj:5 vd:5
-vsubwev_d_w LSX 0111 00000010 00010 vk:5 vj:5 vd:5
-vsubwev_q_d LSX 0111 00000010 00011 vk:5 vj:5 vd:5
-vsubwod_h_b LSX 0111 00000010 01000 vk:5 vj:5 vd:5
-vsubwod_w_h LSX 0111 00000010 01001 vk:5 vj:5 vd:5
-vsubwod_d_w LSX 0111 00000010 01010 vk:5 vj:5 vd:5
-vsubwod_q_d LSX 0111 00000010 01011 vk:5 vj:5 vd:5
-
-vaddwev_h_bu LSX 0111 00000010 11100 vk:5 vj:5 vd:5
-vaddwev_w_hu LSX 0111 00000010 11101 vk:5 vj:5 vd:5
-vaddwev_d_wu LSX 0111 00000010 11110 vk:5 vj:5 vd:5
-vaddwev_q_du LSX 0111 00000010 11111 vk:5 vj:5 vd:5
-vaddwod_h_bu LSX 0111 00000011 00100 vk:5 vj:5 vd:5
-vaddwod_w_hu LSX 0111 00000011 00101 vk:5 vj:5 vd:5
-vaddwod_d_wu LSX 0111 00000011 00110 vk:5 vj:5 vd:5
-vaddwod_q_du LSX 0111 00000011 00111 vk:5 vj:5 vd:5
-
-vsubwev_h_bu LSX 0111 00000011 00000 vk:5 vj:5 vd:5
-vsubwev_w_hu LSX 0111 00000011 00001 vk:5 vj:5 vd:5
-vsubwev_d_wu LSX 0111 00000011 00010 vk:5 vj:5 vd:5
-vsubwev_q_du LSX 0111 00000011 00011 vk:5 vj:5 vd:5
-vsubwod_h_bu LSX 0111 00000011 01000 vk:5 vj:5 vd:5
-vsubwod_w_hu LSX 0111 00000011 01001 vk:5 vj:5 vd:5
-vsubwod_d_wu LSX 0111 00000011 01010 vk:5 vj:5 vd:5
-vsubwod_q_du LSX 0111 00000011 01011 vk:5 vj:5 vd:5
-
-vaddwev_h_bu_b LSX 0111 00000011 11100 vk:5 vj:5 vd:5
-vaddwev_w_hu_h LSX 0111 00000011 11101 vk:5 vj:5 vd:5
-vaddwev_d_wu_w LSX 0111 00000011 11110 vk:5 vj:5 vd:5
-vaddwev_q_du_d LSX 0111 00000011 11111 vk:5 vj:5 vd:5
-vaddwod_h_bu_b LSX 0111 00000100 00000 vk:5 vj:5 vd:5
-vaddwod_w_hu_h LSX 0111 00000100 00001 vk:5 vj:5 vd:5
-vaddwod_d_wu_w LSX 0111 00000100 00010 vk:5 vj:5 vd:5
-vaddwod_q_du_d LSX 0111 00000100 00011 vk:5 vj:5 vd:5
-
-vavg_b LSX 0111 00000110 01000 vk:5 vj:5 vd:5
-vavg_h LSX 0111 00000110 01001 vk:5 vj:5 vd:5
-vavg_w LSX 0111 00000110 01010 vk:5 vj:5 vd:5
-vavg_d LSX 0111 00000110 01011 vk:5 vj:5 vd:5
-vavg_bu LSX 0111 00000110 01100 vk:5 vj:5 vd:5
-vavg_hu LSX 0111 00000110 01101 vk:5 vj:5 vd:5
-vavg_wu LSX 0111 00000110 01110 vk:5 vj:5 vd:5
-vavg_du LSX 0111 00000110 01111 vk:5 vj:5 vd:5
-vavgr_b LSX 0111 00000110 10000 vk:5 vj:5 vd:5
-vavgr_h LSX 0111 00000110 10001 vk:5 vj:5 vd:5
-vavgr_w LSX 0111 00000110 10010 vk:5 vj:5 vd:5
-vavgr_d LSX 0111 00000110 10011 vk:5 vj:5 vd:5
-vavgr_bu LSX 0111 00000110 10100 vk:5 vj:5 vd:5
-vavgr_hu LSX 0111 00000110 10101 vk:5 vj:5 vd:5
-vavgr_wu LSX 0111 00000110 10110 vk:5 vj:5 vd:5
-vavgr_du LSX 0111 00000110 10111 vk:5 vj:5 vd:5
-
-vabsd_b LSX 0111 00000110 00000 vk:5 vj:5 vd:5
-vabsd_h LSX 0111 00000110 00001 vk:5 vj:5 vd:5
-vabsd_w LSX 0111 00000110 00010 vk:5 vj:5 vd:5
-vabsd_d LSX 0111 00000110 00011 vk:5 vj:5 vd:5
-vabsd_bu LSX 0111 00000110 00100 vk:5 vj:5 vd:5
-vabsd_hu LSX 0111 00000110 00101 vk:5 vj:5 vd:5
-vabsd_wu LSX 0111 00000110 00110 vk:5 vj:5 vd:5
-vabsd_du LSX 0111 00000110 00111 vk:5 vj:5 vd:5
-
-vadda_b LSX 0111 00000101 11000 vk:5 vj:5 vd:5
-vadda_h LSX 0111 00000101 11001 vk:5 vj:5 vd:5
-vadda_w LSX 0111 00000101 11010 vk:5 vj:5 vd:5
-vadda_d LSX 0111 00000101 11011 vk:5 vj:5 vd:5
-
-vmax_b LSX 0111 00000111 00000 vk:5 vj:5 vd:5
-vmax_h LSX 0111 00000111 00001 vk:5 vj:5 vd:5
-vmax_w LSX 0111 00000111 00010 vk:5 vj:5 vd:5
-vmax_d LSX 0111 00000111 00011 vk:5 vj:5 vd:5
+vadd_b LSX 0111 00000000 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vadd_h LSX 0111 00000000 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vadd_w LSX 0111 00000000 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vadd_d LSX 0111 00000000 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vadd_q LSX 0111 00010010 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsub_b LSX 0111 00000000 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsub_h LSX 0111 00000000 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsub_w LSX 0111 00000000 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsub_d LSX 0111 00000000 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsub_q LSX 0111 00010010 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vaddi_bu LSX 0111 00101000 10100 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddi_hu LSX 0111 00101000 10101 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddi_wu LSX 0111 00101000 10110 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddi_du LSX 0111 00101000 10111 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubi_bu LSX 0111 00101000 11000 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubi_hu LSX 0111 00101000 11001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubi_wu LSX 0111 00101000 11010 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubi_du LSX 0111 00101000 11011 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vneg_b LSX 0111 00101001 11000 01100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vneg_h LSX 0111 00101001 11000 01101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vneg_w LSX 0111 00101001 11000 01110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vneg_d LSX 0111 00101001 11000 01111 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsadd_b LSX 0111 00000100 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsadd_h LSX 0111 00000100 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsadd_w LSX 0111 00000100 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsadd_d LSX 0111 00000100 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsadd_bu LSX 0111 00000100 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsadd_hu LSX 0111 00000100 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsadd_wu LSX 0111 00000100 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsadd_du LSX 0111 00000100 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vssub_b LSX 0111 00000100 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssub_h LSX 0111 00000100 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssub_w LSX 0111 00000100 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssub_d LSX 0111 00000100 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssub_bu LSX 0111 00000100 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssub_hu LSX 0111 00000100 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssub_wu LSX 0111 00000100 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssub_du LSX 0111 00000100 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vhaddw_h_b LSX 0111 00000101 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhaddw_w_h LSX 0111 00000101 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhaddw_d_w LSX 0111 00000101 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhaddw_q_d LSX 0111 00000101 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhaddw_hu_bu LSX 0111 00000101 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhaddw_wu_hu LSX 0111 00000101 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhaddw_du_wu LSX 0111 00000101 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhaddw_qu_du LSX 0111 00000101 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vhsubw_h_b LSX 0111 00000101 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhsubw_w_h LSX 0111 00000101 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhsubw_d_w LSX 0111 00000101 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhsubw_q_d LSX 0111 00000101 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhsubw_hu_bu LSX 0111 00000101 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhsubw_wu_hu LSX 0111 00000101 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhsubw_du_wu LSX 0111 00000101 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vhsubw_qu_du LSX 0111 00000101 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vaddwev_h_b LSX 0111 00000001 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_w_h LSX 0111 00000001 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_d_w LSX 0111 00000001 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_q_d LSX 0111 00000001 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_h_b LSX 0111 00000010 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_w_h LSX 0111 00000010 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_d_w LSX 0111 00000010 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_q_d LSX 0111 00000010 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsubwev_h_b LSX 0111 00000010 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwev_w_h LSX 0111 00000010 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwev_d_w LSX 0111 00000010 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwev_q_d LSX 0111 00000010 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_h_b LSX 0111 00000010 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_w_h LSX 0111 00000010 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_d_w LSX 0111 00000010 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_q_d LSX 0111 00000010 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vaddwev_h_bu LSX 0111 00000010 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_w_hu LSX 0111 00000010 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_d_wu LSX 0111 00000010 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_q_du LSX 0111 00000010 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_h_bu LSX 0111 00000011 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_w_hu LSX 0111 00000011 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_d_wu LSX 0111 00000011 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_q_du LSX 0111 00000011 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsubwev_h_bu LSX 0111 00000011 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwev_w_hu LSX 0111 00000011 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwev_d_wu LSX 0111 00000011 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwev_q_du LSX 0111 00000011 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_h_bu LSX 0111 00000011 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_w_hu LSX 0111 00000011 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_d_wu LSX 0111 00000011 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsubwod_q_du LSX 0111 00000011 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vaddwev_h_bu_b LSX 0111 00000011 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_w_hu_h LSX 0111 00000011 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_d_wu_w LSX 0111 00000011 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwev_q_du_d LSX 0111 00000011 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_h_bu_b LSX 0111 00000100 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_w_hu_h LSX 0111 00000100 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_d_wu_w LSX 0111 00000100 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vaddwod_q_du_d LSX 0111 00000100 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vavg_b LSX 0111 00000110 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavg_h LSX 0111 00000110 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavg_w LSX 0111 00000110 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavg_d LSX 0111 00000110 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavg_bu LSX 0111 00000110 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavg_hu LSX 0111 00000110 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavg_wu LSX 0111 00000110 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavg_du LSX 0111 00000110 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_b LSX 0111 00000110 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_h LSX 0111 00000110 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_w LSX 0111 00000110 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_d LSX 0111 00000110 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_bu LSX 0111 00000110 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_hu LSX 0111 00000110 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_wu LSX 0111 00000110 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vavgr_du LSX 0111 00000110 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vabsd_b LSX 0111 00000110 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vabsd_h LSX 0111 00000110 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vabsd_w LSX 0111 00000110 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vabsd_d LSX 0111 00000110 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vabsd_bu LSX 0111 00000110 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vabsd_hu LSX 0111 00000110 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vabsd_wu LSX 0111 00000110 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vabsd_du LSX 0111 00000110 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vadda_b LSX 0111 00000101 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vadda_h LSX 0111 00000101 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vadda_w LSX 0111 00000101 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vadda_d LSX 0111 00000101 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vmax_b LSX 0111 00000111 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmax_h LSX 0111 00000111 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmax_w LSX 0111 00000111 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmax_d LSX 0111 00000111 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
vmaxi_b LSX 0111 00101001 00000 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
vmaxi_h LSX 0111 00101001 00001 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
vmaxi_w LSX 0111 00101001 00010 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
vmaxi_d LSX 0111 00101001 00011 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
-
-vmax_bu LSX 0111 00000111 01000 vk:5 vj:5 vd:5
-vmax_hu LSX 0111 00000111 01001 vk:5 vj:5 vd:5
-vmax_wu LSX 0111 00000111 01010 vk:5 vj:5 vd:5
-vmax_du LSX 0111 00000111 01011 vk:5 vj:5 vd:5
-vmaxi_bu LSX 0111 00101001 01000 imm:5 vj:5 vd:5
-vmaxi_hu LSX 0111 00101001 01001 imm:5 vj:5 vd:5
-vmaxi_wu LSX 0111 00101001 01010 imm:5 vj:5 vd:5
-vmaxi_du LSX 0111 00101001 01011 imm:5 vj:5 vd:5
-
-vmin_b LSX 0111 00000111 00100 vk:5 vj:5 vd:5
-vmin_h LSX 0111 00000111 00101 vk:5 vj:5 vd:5
-vmin_w LSX 0111 00000111 00110 vk:5 vj:5 vd:5
-vmin_d LSX 0111 00000111 00111 vk:5 vj:5 vd:5
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
+
+vmax_bu LSX 0111 00000111 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmax_hu LSX 0111 00000111 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmax_wu LSX 0111 00000111 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmax_du LSX 0111 00000111 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaxi_bu LSX 0111 00101001 01000 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaxi_hu LSX 0111 00101001 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaxi_wu LSX 0111 00101001 01010 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaxi_du LSX 0111 00101001 01011 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vmin_b LSX 0111 00000111 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmin_h LSX 0111 00000111 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmin_w LSX 0111 00000111 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmin_d LSX 0111 00000111 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
vmini_b LSX 0111 00101001 00100 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
vmini_h LSX 0111 00101001 00101 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
vmini_w LSX 0111 00101001 00110 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
vmini_d LSX 0111 00101001 00111 imm:5 vj:5 vd:5 \
- !constraints { $imm = sextract($imm, 5);}
-
-vmin_bu LSX 0111 00000111 01100 vk:5 vj:5 vd:5
-vmin_hu LSX 0111 00000111 01101 vk:5 vj:5 vd:5
-vmin_wu LSX 0111 00000111 01110 vk:5 vj:5 vd:5
-vmin_du LSX 0111 00000111 01111 vk:5 vj:5 vd:5
-vmini_bu LSX 0111 00101001 01100 imm:5 vj:5 vd:5
-vmini_hu LSX 0111 00101001 01101 imm:5 vj:5 vd:5
-vmini_wu LSX 0111 00101001 01110 imm:5 vj:5 vd:5
-vmini_du LSX 0111 00101001 01111 imm:5 vj:5 vd:5
-
-vmul_b LSX 0111 00001000 01000 vk:5 vj:5 vd:5
-vmul_h LSX 0111 00001000 01001 vk:5 vj:5 vd:5
-vmul_w LSX 0111 00001000 01010 vk:5 vj:5 vd:5
-vmul_d LSX 0111 00001000 01011 vk:5 vj:5 vd:5
-vmuh_b LSX 0111 00001000 01100 vk:5 vj:5 vd:5
-vmuh_h LSX 0111 00001000 01101 vk:5 vj:5 vd:5
-vmuh_w LSX 0111 00001000 01110 vk:5 vj:5 vd:5
-vmuh_d LSX 0111 00001000 01111 vk:5 vj:5 vd:5
-vmuh_bu LSX 0111 00001000 10000 vk:5 vj:5 vd:5
-vmuh_hu LSX 0111 00001000 10001 vk:5 vj:5 vd:5
-vmuh_wu LSX 0111 00001000 10010 vk:5 vj:5 vd:5
-vmuh_du LSX 0111 00001000 10011 vk:5 vj:5 vd:5
-
-vmulwev_h_b LSX 0111 00001001 00000 vk:5 vj:5 vd:5
-vmulwev_w_h LSX 0111 00001001 00001 vk:5 vj:5 vd:5
-vmulwev_d_w LSX 0111 00001001 00010 vk:5 vj:5 vd:5
-vmulwev_q_d LSX 0111 00001001 00011 vk:5 vj:5 vd:5
-vmulwod_h_b LSX 0111 00001001 00100 vk:5 vj:5 vd:5
-vmulwod_w_h LSX 0111 00001001 00101 vk:5 vj:5 vd:5
-vmulwod_d_w LSX 0111 00001001 00110 vk:5 vj:5 vd:5
-vmulwod_q_d LSX 0111 00001001 00111 vk:5 vj:5 vd:5
-vmulwev_h_bu LSX 0111 00001001 10000 vk:5 vj:5 vd:5
-vmulwev_w_hu LSX 0111 00001001 10001 vk:5 vj:5 vd:5
-vmulwev_d_wu LSX 0111 00001001 10010 vk:5 vj:5 vd:5
-vmulwev_q_du LSX 0111 00001001 10011 vk:5 vj:5 vd:5
-vmulwod_h_bu LSX 0111 00001001 10100 vk:5 vj:5 vd:5
-vmulwod_w_hu LSX 0111 00001001 10101 vk:5 vj:5 vd:5
-vmulwod_d_wu LSX 0111 00001001 10110 vk:5 vj:5 vd:5
-vmulwod_q_du LSX 0111 00001001 10111 vk:5 vj:5 vd:5
-vmulwev_h_bu_b LSX 0111 00001010 00000 vk:5 vj:5 vd:5
-vmulwev_w_hu_h LSX 0111 00001010 00001 vk:5 vj:5 vd:5
-vmulwev_d_wu_w LSX 0111 00001010 00010 vk:5 vj:5 vd:5
-vmulwev_q_du_d LSX 0111 00001010 00011 vk:5 vj:5 vd:5
-vmulwod_h_bu_b LSX 0111 00001010 00100 vk:5 vj:5 vd:5
-vmulwod_w_hu_h LSX 0111 00001010 00101 vk:5 vj:5 vd:5
-vmulwod_d_wu_w LSX 0111 00001010 00110 vk:5 vj:5 vd:5
-vmulwod_q_du_d LSX 0111 00001010 00111 vk:5 vj:5 vd:5
-
-vmadd_b LSX 0111 00001010 10000 vk:5 vj:5 vd:5
-vmadd_h LSX 0111 00001010 10001 vk:5 vj:5 vd:5
-vmadd_w LSX 0111 00001010 10010 vk:5 vj:5 vd:5
-vmadd_d LSX 0111 00001010 10011 vk:5 vj:5 vd:5
-vmsub_b LSX 0111 00001010 10100 vk:5 vj:5 vd:5
-vmsub_h LSX 0111 00001010 10101 vk:5 vj:5 vd:5
-vmsub_w LSX 0111 00001010 10110 vk:5 vj:5 vd:5
-vmsub_d LSX 0111 00001010 10111 vk:5 vj:5 vd:5
-
-vmaddwev_h_b LSX 0111 00001010 11000 vk:5 vj:5 vd:5
-vmaddwev_w_h LSX 0111 00001010 11001 vk:5 vj:5 vd:5
-vmaddwev_d_w LSX 0111 00001010 11010 vk:5 vj:5 vd:5
-vmaddwev_q_d LSX 0111 00001010 11011 vk:5 vj:5 vd:5
-vmaddwod_h_b LSX 0111 00001010 11100 vk:5 vj:5 vd:5
-vmaddwod_w_h LSX 0111 00001010 11101 vk:5 vj:5 vd:5
-vmaddwod_d_w LSX 0111 00001010 11110 vk:5 vj:5 vd:5
-vmaddwod_q_d LSX 0111 00001010 11111 vk:5 vj:5 vd:5
-vmaddwev_h_bu LSX 0111 00001011 01000 vk:5 vj:5 vd:5
-vmaddwev_w_hu LSX 0111 00001011 01001 vk:5 vj:5 vd:5
-vmaddwev_d_wu LSX 0111 00001011 01010 vk:5 vj:5 vd:5
-vmaddwev_q_du LSX 0111 00001011 01011 vk:5 vj:5 vd:5
-vmaddwod_h_bu LSX 0111 00001011 01100 vk:5 vj:5 vd:5
-vmaddwod_w_hu LSX 0111 00001011 01101 vk:5 vj:5 vd:5
-vmaddwod_d_wu LSX 0111 00001011 01110 vk:5 vj:5 vd:5
-vmaddwod_q_du LSX 0111 00001011 01111 vk:5 vj:5 vd:5
-vmaddwev_h_bu_b LSX 0111 00001011 11000 vk:5 vj:5 vd:5
-vmaddwev_w_hu_h LSX 0111 00001011 11001 vk:5 vj:5 vd:5
-vmaddwev_d_wu_w LSX 0111 00001011 11010 vk:5 vj:5 vd:5
-vmaddwev_q_du_d LSX 0111 00001011 11011 vk:5 vj:5 vd:5
-vmaddwod_h_bu_b LSX 0111 00001011 11100 vk:5 vj:5 vd:5
-vmaddwod_w_hu_h LSX 0111 00001011 11101 vk:5 vj:5 vd:5
-vmaddwod_d_wu_w LSX 0111 00001011 11110 vk:5 vj:5 vd:5
-vmaddwod_q_du_d LSX 0111 00001011 11111 vk:5 vj:5 vd:5
-
-vdiv_b LSX 0111 00001110 00000 vk:5 vj:5 vd:5
-vdiv_h LSX 0111 00001110 00001 vk:5 vj:5 vd:5
-vdiv_w LSX 0111 00001110 00010 vk:5 vj:5 vd:5
-vdiv_d LSX 0111 00001110 00011 vk:5 vj:5 vd:5
-vdiv_bu LSX 0111 00001110 01000 vk:5 vj:5 vd:5
-vdiv_hu LSX 0111 00001110 01001 vk:5 vj:5 vd:5
-vdiv_wu LSX 0111 00001110 01010 vk:5 vj:5 vd:5
-vdiv_du LSX 0111 00001110 01011 vk:5 vj:5 vd:5
-vmod_b LSX 0111 00001110 00100 vk:5 vj:5 vd:5
-vmod_h LSX 0111 00001110 00101 vk:5 vj:5 vd:5
-vmod_w LSX 0111 00001110 00110 vk:5 vj:5 vd:5
-vmod_d LSX 0111 00001110 00111 vk:5 vj:5 vd:5
-vmod_bu LSX 0111 00001110 01100 vk:5 vj:5 vd:5
-vmod_hu LSX 0111 00001110 01101 vk:5 vj:5 vd:5
-vmod_wu LSX 0111 00001110 01110 vk:5 vj:5 vd:5
-vmod_du LSX 0111 00001110 01111 vk:5 vj:5 vd:5
-
-vsat_b LSX 0111 00110010 01000 01 imm:3 vj:5 vd:5
-vsat_h LSX 0111 00110010 01000 1 imm:4 vj:5 vd:5
-vsat_w LSX 0111 00110010 01001 imm:5 vj:5 vd:5
-vsat_d LSX 0111 00110010 0101 imm:6 vj:5 vd:5
-vsat_bu LSX 0111 00110010 10000 01 imm:3 vj:5 vd:5
-vsat_hu LSX 0111 00110010 10000 1 imm:4 vj:5 vd:5
-vsat_wu LSX 0111 00110010 10001 imm:5 vj:5 vd:5
-vsat_du LSX 0111 00110010 1001 imm:6 vj:5 vd:5
-
-vexth_h_b LSX 0111 00101001 11101 11000 vj:5 vd:5
-vexth_w_h LSX 0111 00101001 11101 11001 vj:5 vd:5
-vexth_d_w LSX 0111 00101001 11101 11010 vj:5 vd:5
-vexth_q_d LSX 0111 00101001 11101 11011 vj:5 vd:5
-vexth_hu_bu LSX 0111 00101001 11101 11100 vj:5 vd:5
-vexth_wu_hu LSX 0111 00101001 11101 11101 vj:5 vd:5
-vexth_du_wu LSX 0111 00101001 11101 11110 vj:5 vd:5
-vexth_qu_du LSX 0111 00101001 11101 11111 vj:5 vd:5
-
-vsigncov_b LSX 0111 00010010 11100 vk:5 vj:5 vd:5
-vsigncov_h LSX 0111 00010010 11101 vk:5 vj:5 vd:5
-vsigncov_w LSX 0111 00010010 11110 vk:5 vj:5 vd:5
-vsigncov_d LSX 0111 00010010 11111 vk:5 vj:5 vd:5
-
-vmskltz_b LSX 0111 00101001 11000 10000 vj:5 vd:5
-vmskltz_h LSX 0111 00101001 11000 10001 vj:5 vd:5
-vmskltz_w LSX 0111 00101001 11000 10010 vj:5 vd:5
-vmskltz_d LSX 0111 00101001 11000 10011 vj:5 vd:5
-vmskgez_b LSX 0111 00101001 11000 10100 vj:5 vd:5
-vmsknz_b LSX 0111 00101001 11000 11000 vj:5 vd:5
-
-vand_v LSX 0111 00010010 01100 vk:5 vj:5 vd:5
-vor_v LSX 0111 00010010 01101 vk:5 vj:5 vd:5
-vxor_v LSX 0111 00010010 01110 vk:5 vj:5 vd:5
-vnor_v LSX 0111 00010010 01111 vk:5 vj:5 vd:5
-vandn_v LSX 0111 00010010 10000 vk:5 vj:5 vd:5
-vorn_v LSX 0111 00010010 10001 vk:5 vj:5 vd:5
-
-vandi_b LSX 0111 00111101 00 imm:8 vj:5 vd:5
-vori_b LSX 0111 00111101 01 imm:8 vj:5 vd:5
-vxori_b LSX 0111 00111101 10 imm:8 vj:5 vd:5
-vnori_b LSX 0111 00111101 11 imm:8 vj:5 vd:5
-
-vsll_b LSX 0111 00001110 10000 vk:5 vj:5 vd:5
-vsll_h LSX 0111 00001110 10001 vk:5 vj:5 vd:5
-vsll_w LSX 0111 00001110 10010 vk:5 vj:5 vd:5
-vsll_d LSX 0111 00001110 10011 vk:5 vj:5 vd:5
-vslli_b LSX 0111 00110010 11000 01 imm:3 vj:5 vd:5
-vslli_h LSX 0111 00110010 11000 1 imm:4 vj:5 vd:5
-vslli_w LSX 0111 00110010 11001 imm:5 vj:5 vd:5
-vslli_d LSX 0111 00110010 1101 imm:6 vj:5 vd:5
-
-vsrl_b LSX 0111 00001110 10100 vk:5 vj:5 vd:5
-vsrl_h LSX 0111 00001110 10101 vk:5 vj:5 vd:5
-vsrl_w LSX 0111 00001110 10110 vk:5 vj:5 vd:5
-vsrl_d LSX 0111 00001110 10111 vk:5 vj:5 vd:5
-vsrli_b LSX 0111 00110011 00000 01 imm:3 vj:5 vd:5
-vsrli_h LSX 0111 00110011 00000 1 imm:4 vj:5 vd:5
-vsrli_w LSX 0111 00110011 00001 imm:5 vj:5 vd:5
-vsrli_d LSX 0111 00110011 0001 imm:6 vj:5 vd:5
-
-vsra_b LSX 0111 00001110 11000 vk:5 vj:5 vd:5
-vsra_h LSX 0111 00001110 11001 vk:5 vj:5 vd:5
-vsra_w LSX 0111 00001110 11010 vk:5 vj:5 vd:5
-vsra_d LSX 0111 00001110 11011 vk:5 vj:5 vd:5
-vsrai_b LSX 0111 00110011 01000 01 imm:3 vj:5 vd:5
-vsrai_h LSX 0111 00110011 01000 1 imm:4 vj:5 vd:5
-vsrai_w LSX 0111 00110011 01001 imm:5 vj:5 vd:5
-vsrai_d LSX 0111 00110011 0101 imm:6 vj:5 vd:5
-
-vrotr_b LSX 0111 00001110 11100 vk:5 vj:5 vd:5
-vrotr_h LSX 0111 00001110 11101 vk:5 vj:5 vd:5
-vrotr_w LSX 0111 00001110 11110 vk:5 vj:5 vd:5
-vrotr_d LSX 0111 00001110 11111 vk:5 vj:5 vd:5
-vrotri_b LSX 0111 00101010 00000 01 imm:3 vj:5 vd:5
-vrotri_h LSX 0111 00101010 00000 1 imm:4 vj:5 vd:5
-vrotri_w LSX 0111 00101010 00001 imm:5 vj:5 vd:5
-vrotri_d LSX 0111 00101010 0001 imm:6 vj:5 vd:5
-
-vsllwil_h_b LSX 0111 00110000 10000 01 imm:3 vj:5 vd:5
-vsllwil_w_h LSX 0111 00110000 10000 1 imm:4 vj:5 vd:5
-vsllwil_d_w LSX 0111 00110000 10001 imm:5 vj:5 vd:5
-vextl_q_d LSX 0111 00110000 10010 00000 vj:5 vd:5
-vsllwil_hu_bu LSX 0111 00110000 11000 01 imm:3 vj:5 vd:5
-vsllwil_wu_hu LSX 0111 00110000 11000 1 imm:4 vj:5 vd:5
-vsllwil_du_wu LSX 0111 00110000 11001 imm:5 vj:5 vd:5
-vextl_qu_du LSX 0111 00110000 11010 00000 vj:5 vd:5
-
-vsrlr_b LSX 0111 00001111 00000 vk:5 vj:5 vd:5
-vsrlr_h LSX 0111 00001111 00001 vk:5 vj:5 vd:5
-vsrlr_w LSX 0111 00001111 00010 vk:5 vj:5 vd:5
-vsrlr_d LSX 0111 00001111 00011 vk:5 vj:5 vd:5
-vsrlri_b LSX 0111 00101010 01000 01 imm:3 vj:5 vd:5
-vsrlri_h LSX 0111 00101010 01000 1 imm:4 vj:5 vd:5
-vsrlri_w LSX 0111 00101010 01001 imm:5 vj:5 vd:5
-vsrlri_d LSX 0111 00101010 0101 imm:6 vj:5 vd:5
-
-vsrar_b LSX 0111 00001111 00100 vk:5 vj:5 vd:5
-vsrar_h LSX 0111 00001111 00101 vk:5 vj:5 vd:5
-vsrar_w LSX 0111 00001111 00110 vk:5 vj:5 vd:5
-vsrar_d LSX 0111 00001111 00111 vk:5 vj:5 vd:5
-vsrari_b LSX 0111 00101010 10000 01 imm:3 vj:5 vd:5
-vsrari_h LSX 0111 00101010 10000 1 imm:4 vj:5 vd:5
-vsrari_w LSX 0111 00101010 10001 imm:5 vj:5 vd:5
-vsrari_d LSX 0111 00101010 1001 imm:6 vj:5 vd:5
-
-vsrln_b_h LSX 0111 00001111 01001 vk:5 vj:5 vd:5
-vsrln_h_w LSX 0111 00001111 01010 vk:5 vj:5 vd:5
-vsrln_w_d LSX 0111 00001111 01011 vk:5 vj:5 vd:5
-vsran_b_h LSX 0111 00001111 01101 vk:5 vj:5 vd:5
-vsran_h_w LSX 0111 00001111 01110 vk:5 vj:5 vd:5
-vsran_w_d LSX 0111 00001111 01111 vk:5 vj:5 vd:5
-
-vsrlni_b_h LSX 0111 00110100 00000 1 imm:4 vj:5 vd:5
-vsrlni_h_w LSX 0111 00110100 00001 imm:5 vj:5 vd:5
-vsrlni_w_d LSX 0111 00110100 0001 imm:6 vj:5 vd:5
-vsrlni_d_q LSX 0111 00110100 001 imm:7 vj:5 vd:5
-vsrani_b_h LSX 0111 00110101 10000 1 imm:4 vj:5 vd:5
-vsrani_h_w LSX 0111 00110101 10001 imm:5 vj:5 vd:5
-vsrani_w_d LSX 0111 00110101 1001 imm:6 vj:5 vd:5
-vsrani_d_q LSX 0111 00110101 101 imm:7 vj:5 vd:5
-
-vsrlrn_b_h LSX 0111 00001111 10001 vk:5 vj:5 vd:5
-vsrlrn_h_w LSX 0111 00001111 10010 vk:5 vj:5 vd:5
-vsrlrn_w_d LSX 0111 00001111 10011 vk:5 vj:5 vd:5
-vsrarn_b_h LSX 0111 00001111 10101 vk:5 vj:5 vd:5
-vsrarn_h_w LSX 0111 00001111 10110 vk:5 vj:5 vd:5
-vsrarn_w_d LSX 0111 00001111 10111 vk:5 vj:5 vd:5
-
-vsrlrni_b_h LSX 0111 00110100 01000 1 imm:4 vj:5 vd:5
-vsrlrni_h_w LSX 0111 00110100 01001 imm:5 vj:5 vd:5
-vsrlrni_w_d LSX 0111 00110100 0101 imm:6 vj:5 vd:5
-vsrlrni_d_q LSX 0111 00110100 011 imm:7 vj:5 vd:5
-vsrarni_b_h LSX 0111 00110101 11000 1 imm:4 vj:5 vd:5
-vsrarni_h_w LSX 0111 00110101 11001 imm:5 vj:5 vd:5
-vsrarni_w_d LSX 0111 00110101 1101 imm:6 vj:5 vd:5
-vsrarni_d_q LSX 0111 00110101 111 imm:7 vj:5 vd:5
-
-vssrln_b_h LSX 0111 00001111 11001 vk:5 vj:5 vd:5
-vssrln_h_w LSX 0111 00001111 11010 vk:5 vj:5 vd:5
-vssrln_w_d LSX 0111 00001111 11011 vk:5 vj:5 vd:5
-vssran_b_h LSX 0111 00001111 11101 vk:5 vj:5 vd:5
-vssran_h_w LSX 0111 00001111 11110 vk:5 vj:5 vd:5
-vssran_w_d LSX 0111 00001111 11111 vk:5 vj:5 vd:5
-vssrln_bu_h LSX 0111 00010000 01001 vk:5 vj:5 vd:5
-vssrln_hu_w LSX 0111 00010000 01010 vk:5 vj:5 vd:5
-vssrln_wu_d LSX 0111 00010000 01011 vk:5 vj:5 vd:5
-vssran_bu_h LSX 0111 00010000 01101 vk:5 vj:5 vd:5
-vssran_hu_w LSX 0111 00010000 01110 vk:5 vj:5 vd:5
-vssran_wu_d LSX 0111 00010000 01111 vk:5 vj:5 vd:5
-
-vssrlni_b_h LSX 0111 00110100 10000 1 imm:4 vj:5 vd:5
-vssrlni_h_w LSX 0111 00110100 10001 imm:5 vj:5 vd:5
-vssrlni_w_d LSX 0111 00110100 1001 imm:6 vj:5 vd:5
-vssrlni_d_q LSX 0111 00110100 101 imm:7 vj:5 vd:5
-vssrani_b_h LSX 0111 00110110 00000 1 imm:4 vj:5 vd:5
-vssrani_h_w LSX 0111 00110110 00001 imm:5 vj:5 vd:5
-vssrani_w_d LSX 0111 00110110 0001 imm:6 vj:5 vd:5
-vssrani_d_q LSX 0111 00110110 001 imm:7 vj:5 vd:5
-vssrlni_bu_h LSX 0111 00110100 11000 1 imm:4 vj:5 vd:5
-vssrlni_hu_w LSX 0111 00110100 11001 imm:5 vj:5 vd:5
-vssrlni_wu_d LSX 0111 00110100 1101 imm:6 vj:5 vd:5
-vssrlni_du_q LSX 0111 00110100 111 imm:7 vj:5 vd:5
-vssrani_bu_h LSX 0111 00110110 01000 1 imm:4 vj:5 vd:5
-vssrani_hu_w LSX 0111 00110110 01001 imm:5 vj:5 vd:5
-vssrani_wu_d LSX 0111 00110110 0101 imm:6 vj:5 vd:5
-vssrani_du_q LSX 0111 00110110 011 imm:7 vj:5 vd:5
-
-vssrlrn_b_h LSX 0111 00010000 00001 vk:5 vj:5 vd:5
-vssrlrn_h_w LSX 0111 00010000 00010 vk:5 vj:5 vd:5
-vssrlrn_w_d LSX 0111 00010000 00011 vk:5 vj:5 vd:5
-vssrarn_b_h LSX 0111 00010000 00101 vk:5 vj:5 vd:5
-vssrarn_h_w LSX 0111 00010000 00110 vk:5 vj:5 vd:5
-vssrarn_w_d LSX 0111 00010000 00111 vk:5 vj:5 vd:5
-vssrlrn_bu_h LSX 0111 00010000 10001 vk:5 vj:5 vd:5
-vssrlrn_hu_w LSX 0111 00010000 10010 vk:5 vj:5 vd:5
-vssrlrn_wu_d LSX 0111 00010000 10011 vk:5 vj:5 vd:5
-vssrarn_bu_h LSX 0111 00010000 10101 vk:5 vj:5 vd:5
-vssrarn_hu_w LSX 0111 00010000 10110 vk:5 vj:5 vd:5
-vssrarn_wu_d LSX 0111 00010000 10111 vk:5 vj:5 vd:5
-
-vssrlrni_b_h LSX 0111 00110101 00000 1 imm:4 vj:5 vd:5
-vssrlrni_h_w LSX 0111 00110101 00001 imm:5 vj:5 vd:5
-vssrlrni_w_d LSX 0111 00110101 0001 imm:6 vj:5 vd:5
-vssrlrni_d_q LSX 0111 00110101 001 imm:7 vj:5 vd:5
-vssrarni_b_h LSX 0111 00110110 10000 1 imm:4 vj:5 vd:5
-vssrarni_h_w LSX 0111 00110110 10001 imm:5 vj:5 vd:5
-vssrarni_w_d LSX 0111 00110110 1001 imm:6 vj:5 vd:5
-vssrarni_d_q LSX 0111 00110110 101 imm:7 vj:5 vd:5
-vssrlrni_hu_w LSX 0111 00110101 01001 imm:5 vj:5 vd:5
-vssrlrni_wu_d LSX 0111 00110101 0101 imm:6 vj:5 vd:5
-vssrlrni_du_q LSX 0111 00110101 011 imm:7 vj:5 vd:5
-vssrarni_bu_h LSX 0111 00110110 11000 1 imm:4 vj:5 vd:5
-vssrarni_hu_w LSX 0111 00110110 11001 imm:5 vj:5 vd:5
-vssrarni_wu_d LSX 0111 00110110 1101 imm:6 vj:5 vd:5
-vssrarni_du_q LSX 0111 00110110 111 imm:7 vj:5 vd:5
-
-vclo_b LSX 0111 00101001 11000 00000 vj:5 vd:5
-vclo_h LSX 0111 00101001 11000 00001 vj:5 vd:5
-vclo_w LSX 0111 00101001 11000 00010 vj:5 vd:5
-vclo_d LSX 0111 00101001 11000 00011 vj:5 vd:5
-vclz_b LSX 0111 00101001 11000 00100 vj:5 vd:5
-vclz_h LSX 0111 00101001 11000 00101 vj:5 vd:5
-vclz_w LSX 0111 00101001 11000 00110 vj:5 vd:5
-vclz_d LSX 0111 00101001 11000 00111 vj:5 vd:5
-
-vpcnt_b LSX 0111 00101001 11000 01000 vj:5 vd:5
-vpcnt_h LSX 0111 00101001 11000 01001 vj:5 vd:5
-vpcnt_w LSX 0111 00101001 11000 01010 vj:5 vd:5
-vpcnt_d LSX 0111 00101001 11000 01011 vj:5 vd:5
-
-vbitclr_b LSX 0111 00010000 11000 vk:5 vj:5 vd:5
-vbitclr_h LSX 0111 00010000 11001 vk:5 vj:5 vd:5
-vbitclr_w LSX 0111 00010000 11010 vk:5 vj:5 vd:5
-vbitclr_d LSX 0111 00010000 11011 vk:5 vj:5 vd:5
-vbitclri_b LSX 0111 00110001 00000 01 imm:3 vj:5 vd:5
-vbitclri_h LSX 0111 00110001 00000 1 imm:4 vj:5 vd:5
-vbitclri_w LSX 0111 00110001 00001 imm:5 vj:5 vd:5
-vbitclri_d LSX 0111 00110001 0001 imm:6 vj:5 vd:5
-vbitset_b LSX 0111 00010000 11100 vk:5 vj:5 vd:5
-vbitset_h LSX 0111 00010000 11101 vk:5 vj:5 vd:5
-vbitset_w LSX 0111 00010000 11110 vk:5 vj:5 vd:5
-vbitset_d LSX 0111 00010000 11111 vk:5 vj:5 vd:5
-vbitseti_b LSX 0111 00110001 01000 01 imm:3 vj:5 vd:5
-vbitseti_h LSX 0111 00110001 01000 1 imm:4 vj:5 vd:5
-vbitseti_w LSX 0111 00110001 01001 imm:5 vj:5 vd:5
-vbitseti_d LSX 0111 00110001 0101 imm:6 vj:5 vd:5
-vbitrev_b LSX 0111 00010001 00000 vk:5 vj:5 vd:5
-vbitrev_h LSX 0111 00010001 00001 vk:5 vj:5 vd:5
-vbitrev_w LSX 0111 00010001 00010 vk:5 vj:5 vd:5
-vbitrev_d LSX 0111 00010001 00011 vk:5 vj:5 vd:5
-vbitrevi_b LSX 0111 00110001 10000 01 imm:3 vj:5 vd:5
-vbitrevi_h LSX 0111 00110001 10000 1 imm:4 vj:5 vd:5
-vbitrevi_w LSX 0111 00110001 10001 imm:5 vj:5 vd:5
-vbitrevi_d LSX 0111 00110001 1001 imm:6 vj:5 vd:5
-
-vfrstp_b LSX 0111 00010010 10110 vk:5 vj:5 vd:5
-vfrstp_h LSX 0111 00010010 10111 vk:5 vj:5 vd:5
-vfrstpi_b LSX 0111 00101001 10100 imm:5 vj:5 vd:5
-vfrstpi_h LSX 0111 00101001 10101 imm:5 vj:5 vd:5
-
-vfadd_s LSX 0111 00010011 00001 vk:5 vj:5 vd:5
-vfadd_d LSX 0111 00010011 00010 vk:5 vj:5 vd:5
-vfsub_s LSX 0111 00010011 00101 vk:5 vj:5 vd:5
-vfsub_d LSX 0111 00010011 00110 vk:5 vj:5 vd:5
-vfmul_s LSX 0111 00010011 10001 vk:5 vj:5 vd:5
-vfmul_d LSX 0111 00010011 10010 vk:5 vj:5 vd:5
-vfdiv_s LSX 0111 00010011 10101 vk:5 vj:5 vd:5
-vfdiv_d LSX 0111 00010011 10110 vk:5 vj:5 vd:5
-
-vfmadd_s LSX 0000 10010001 va:5 vk:5 vj:5 vd:5
-vfmadd_d LSX 0000 10010010 va:5 vk:5 vj:5 vd:5
-vfmsub_s LSX 0000 10010101 va:5 vk:5 vj:5 vd:5
-vfmsub_d LSX 0000 10010110 va:5 vk:5 vj:5 vd:5
-vfnmadd_s LSX 0000 10011001 va:5 vk:5 vj:5 vd:5
-vfnmadd_d LSX 0000 10011010 va:5 vk:5 vj:5 vd:5
-vfnmsub_s LSX 0000 10011101 va:5 vk:5 vj:5 vd:5
-vfnmsub_d LSX 0000 10011110 va:5 vk:5 vj:5 vd:5
-
-vfmax_s LSX 0111 00010011 11001 vk:5 vj:5 vd:5
-vfmax_d LSX 0111 00010011 11010 vk:5 vj:5 vd:5
-vfmin_s LSX 0111 00010011 11101 vk:5 vj:5 vd:5
-vfmin_d LSX 0111 00010011 11110 vk:5 vj:5 vd:5
-
-vfmaxa_s LSX 0111 00010100 00001 vk:5 vj:5 vd:5
-vfmaxa_d LSX 0111 00010100 00010 vk:5 vj:5 vd:5
-vfmina_s LSX 0111 00010100 00101 vk:5 vj:5 vd:5
-vfmina_d LSX 0111 00010100 00110 vk:5 vj:5 vd:5
-
-vflogb_s LSX 0111 00101001 11001 10001 vj:5 vd:5
-vflogb_d LSX 0111 00101001 11001 10010 vj:5 vd:5
-
-vfclass_s LSX 0111 00101001 11001 10101 vj:5 vd:5
-vfclass_d LSX 0111 00101001 11001 10110 vj:5 vd:5
-
-vfsqrt_s LSX 0111 00101001 11001 11001 vj:5 vd:5
-vfsqrt_d LSX 0111 00101001 11001 11010 vj:5 vd:5
-vfrecip_s LSX 0111 00101001 11001 11101 vj:5 vd:5
-vfrecip_d LSX 0111 00101001 11001 11110 vj:5 vd:5
-vfrsqrt_s LSX 0111 00101001 11010 00001 vj:5 vd:5
-vfrsqrt_d LSX 0111 00101001 11010 00010 vj:5 vd:5
-
-vfcvtl_s_h LSX 0111 00101001 11011 11010 vj:5 vd:5
-vfcvth_s_h LSX 0111 00101001 11011 11011 vj:5 vd:5
-vfcvtl_d_s LSX 0111 00101001 11011 11100 vj:5 vd:5
-vfcvth_d_s LSX 0111 00101001 11011 11101 vj:5 vd:5
-vfcvt_h_s LSX 0111 00010100 01100 vk:5 vj:5 vd:5
-vfcvt_s_d LSX 0111 00010100 01101 vk:5 vj:5 vd:5
-
-vfrint_s LSX 0111 00101001 11010 01101 vj:5 vd:5
-vfrint_d LSX 0111 00101001 11010 01110 vj:5 vd:5
-vfrintrm_s LSX 0111 00101001 11010 10001 vj:5 vd:5
-vfrintrm_d LSX 0111 00101001 11010 10010 vj:5 vd:5
-vfrintrp_s LSX 0111 00101001 11010 10101 vj:5 vd:5
-vfrintrp_d LSX 0111 00101001 11010 10110 vj:5 vd:5
-vfrintrz_s LSX 0111 00101001 11010 11001 vj:5 vd:5
-vfrintrz_d LSX 0111 00101001 11010 11010 vj:5 vd:5
-vfrintrne_s LSX 0111 00101001 11010 11101 vj:5 vd:5
-vfrintrne_d LSX 0111 00101001 11010 11110 vj:5 vd:5
-
-vftint_w_s LSX 0111 00101001 11100 01100 vj:5 vd:5
-vftint_l_d LSX 0111 00101001 11100 01101 vj:5 vd:5
-vftintrm_w_s LSX 0111 00101001 11100 01110 vj:5 vd:5
-vftintrm_l_d LSX 0111 00101001 11100 01111 vj:5 vd:5
-vftintrp_w_s LSX 0111 00101001 11100 10000 vj:5 vd:5
-vftintrp_l_d LSX 0111 00101001 11100 10001 vj:5 vd:5
-vftintrz_w_s LSX 0111 00101001 11100 10010 vj:5 vd:5
-vftintrz_l_d LSX 0111 00101001 11100 10011 vj:5 vd:5
-vftintrne_w_s LSX 0111 00101001 11100 10100 vj:5 vd:5
-vftintrne_l_d LSX 0111 00101001 11100 10101 vj:5 vd:5
-vftint_wu_s LSX 0111 00101001 11100 10110 vj:5 vd:5
-vftint_lu_d LSX 0111 00101001 11100 10111 vj:5 vd:5
-vftintrz_wu_s LSX 0111 00101001 11100 11100 vj:5 vd:5
-vftintrz_lu_d LSX 0111 00101001 11100 11101 vj:5 vd:5
-vftint_w_d LSX 0111 00010100 10011 vk:5 vj:5 vd:5
-vftintrm_w_d LSX 0111 00010100 10100 vk:5 vj:5 vd:5
-vftintrp_w_d LSX 0111 00010100 10101 vk:5 vj:5 vd:5
-vftintrz_w_d LSX 0111 00010100 10110 vk:5 vj:5 vd:5
-vftintrne_w_d LSX 0111 00010100 10111 vk:5 vj:5 vd:5
-vftintl_l_s LSX 0111 00101001 11101 00000 vj:5 vd:5
-vftinth_l_s LSX 0111 00101001 11101 00001 vj:5 vd:5
-vftintrml_l_s LSX 0111 00101001 11101 00010 vj:5 vd:5
-vftintrmh_l_s LSX 0111 00101001 11101 00011 vj:5 vd:5
-vftintrpl_l_s LSX 0111 00101001 11101 00100 vj:5 vd:5
-vftintrph_l_s LSX 0111 00101001 11101 00101 vj:5 vd:5
-vftintrzl_l_s LSX 0111 00101001 11101 00110 vj:5 vd:5
-vftintrzh_l_s LSX 0111 00101001 11101 00111 vj:5 vd:5
-vftintrnel_l_s LSX 0111 00101001 11101 01000 vj:5 vd:5
-vftintrneh_l_s LSX 0111 00101001 11101 01001 vj:5 vd:5
-
-vffint_s_w LSX 0111 00101001 11100 00000 vj:5 vd:5
-vffint_s_wu LSX 0111 00101001 11100 00001 vj:5 vd:5
-vffint_d_l LSX 0111 00101001 11100 00010 vj:5 vd:5
-vffint_d_lu LSX 0111 00101001 11100 00011 vj:5 vd:5
-vffintl_d_w LSX 0111 00101001 11100 00100 vj:5 vd:5
-vffinth_d_w LSX 0111 00101001 11100 00101 vj:5 vd:5
-vffint_s_l LSX 0111 00010100 10000 vk:5 vj:5 vd:5
-
-vseq_b LSX 0111 00000000 00000 vk:5 vj:5 vd:5
-vseq_h LSX 0111 00000000 00001 vk:5 vj:5 vd:5
-vseq_w LSX 0111 00000000 00010 vk:5 vj:5 vd:5
-vseq_d LSX 0111 00000000 00011 vk:5 vj:5 vd:5
-vseqi_b LSX 0111 00101000 00000 imm:5 vj:5 vd:5
-vseqi_h LSX 0111 00101000 00001 imm:5 vj:5 vd:5
-vseqi_w LSX 0111 00101000 00010 imm:5 vj:5 vd:5
-vseqi_d LSX 0111 00101000 00011 imm:5 vj:5 vd:5
-
-vsle_b LSX 0111 00000000 00100 vk:5 vj:5 vd:5
-vsle_h LSX 0111 00000000 00101 vk:5 vj:5 vd:5
-vsle_w LSX 0111 00000000 00110 vk:5 vj:5 vd:5
-vsle_d LSX 0111 00000000 00111 vk:5 vj:5 vd:5
-vslei_b LSX 0111 00101000 00100 imm:5 vj:5 vd:5
-vslei_h LSX 0111 00101000 00101 imm:5 vj:5 vd:5
-vslei_w LSX 0111 00101000 00110 imm:5 vj:5 vd:5
-vslei_d LSX 0111 00101000 00111 imm:5 vj:5 vd:5
-vsle_bu LSX 0111 00000000 01000 vk:5 vj:5 vd:5
-vsle_hu LSX 0111 00000000 01001 vk:5 vj:5 vd:5
-vsle_wu LSX 0111 00000000 01010 vk:5 vj:5 vd:5
-vsle_du LSX 0111 00000000 01011 vk:5 vj:5 vd:5
-vslei_bu LSX 0111 00101000 01000 imm:5 vj:5 vd:5
-vslei_hu LSX 0111 00101000 01000 imm:5 vj:5 vd:5
-vslei_wu LSX 0111 00101000 01010 imm:5 vj:5 vd:5
-vslei_du LSX 0111 00101000 01010 imm:5 vj:5 vd:5
-
-vslt_b LSX 0111 00000000 01100 vk:5 vj:5 vd:5
-vslt_h LSX 0111 00000000 01101 vk:5 vj:5 vd:5
-vslt_w LSX 0111 00000000 01110 vk:5 vj:5 vd:5
-vslt_d LSX 0111 00000000 01111 vk:5 vj:5 vd:5
-vslti_b LSX 0111 00101000 01100 imm:5 vj:5 vd:5
-vslti_h LSX 0111 00101000 01101 imm:5 vj:5 vd:5
-vslti_w LSX 0111 00101000 01110 imm:5 vj:5 vd:5
-vslti_d LSX 0111 00101000 01111 imm:5 vj:5 vd:5
-vslt_bu LSX 0111 00000000 10000 vk:5 vj:5 vd:5
-vslt_hu LSX 0111 00000000 10001 vk:5 vj:5 vd:5
-vslt_wu LSX 0111 00000000 10010 vk:5 vj:5 vd:5
-vslt_du LSX 0111 00000000 10011 vk:5 vj:5 vd:5
-vslti_bu LSX 0111 00101000 10000 imm:5 vj:5 vd:5
-vslti_hu LSX 0111 00101000 10001 imm:5 vj:5 vd:5
-vslti_wu LSX 0111 00101000 10010 imm:5 vj:5 vd:5
-vslti_du LSX 0111 00101000 10011 imm:5 vj:5 vd:5
+ !constraints { $imm = sextract($imm, 5);} \
+ !clean { clean_lsx_result($vd); }
+
+vmin_bu LSX 0111 00000111 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmin_hu LSX 0111 00000111 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmin_wu LSX 0111 00000111 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmin_du LSX 0111 00000111 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmini_bu LSX 0111 00101001 01100 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmini_hu LSX 0111 00101001 01101 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmini_wu LSX 0111 00101001 01110 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmini_du LSX 0111 00101001 01111 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vmul_b LSX 0111 00001000 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmul_h LSX 0111 00001000 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmul_w LSX 0111 00001000 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmul_d LSX 0111 00001000 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_b LSX 0111 00001000 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_h LSX 0111 00001000 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_w LSX 0111 00001000 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_d LSX 0111 00001000 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_bu LSX 0111 00001000 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_hu LSX 0111 00001000 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_wu LSX 0111 00001000 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmuh_du LSX 0111 00001000 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vmulwev_h_b LSX 0111 00001001 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_w_h LSX 0111 00001001 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_d_w LSX 0111 00001001 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_q_d LSX 0111 00001001 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_h_b LSX 0111 00001001 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_w_h LSX 0111 00001001 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_d_w LSX 0111 00001001 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_q_d LSX 0111 00001001 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_h_bu LSX 0111 00001001 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_w_hu LSX 0111 00001001 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_d_wu LSX 0111 00001001 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_q_du LSX 0111 00001001 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_h_bu LSX 0111 00001001 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_w_hu LSX 0111 00001001 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_d_wu LSX 0111 00001001 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_q_du LSX 0111 00001001 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_h_bu_b LSX 0111 00001010 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_w_hu_h LSX 0111 00001010 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_d_wu_w LSX 0111 00001010 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwev_q_du_d LSX 0111 00001010 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_h_bu_b LSX 0111 00001010 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_w_hu_h LSX 0111 00001010 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_d_wu_w LSX 0111 00001010 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmulwod_q_du_d LSX 0111 00001010 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vmadd_b LSX 0111 00001010 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmadd_h LSX 0111 00001010 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmadd_w LSX 0111 00001010 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmadd_d LSX 0111 00001010 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmsub_b LSX 0111 00001010 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmsub_h LSX 0111 00001010 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmsub_w LSX 0111 00001010 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmsub_d LSX 0111 00001010 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vmaddwev_h_b LSX 0111 00001010 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_w_h LSX 0111 00001010 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_d_w LSX 0111 00001010 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_q_d LSX 0111 00001010 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_h_b LSX 0111 00001010 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_w_h LSX 0111 00001010 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_d_w LSX 0111 00001010 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_q_d LSX 0111 00001010 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_h_bu LSX 0111 00001011 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_w_hu LSX 0111 00001011 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_d_wu LSX 0111 00001011 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_q_du LSX 0111 00001011 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_h_bu LSX 0111 00001011 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_w_hu LSX 0111 00001011 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_d_wu LSX 0111 00001011 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_q_du LSX 0111 00001011 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_h_bu_b LSX 0111 00001011 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_w_hu_h LSX 0111 00001011 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_d_wu_w LSX 0111 00001011 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwev_q_du_d LSX 0111 00001011 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_h_bu_b LSX 0111 00001011 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_w_hu_h LSX 0111 00001011 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_d_wu_w LSX 0111 00001011 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmaddwod_q_du_d LSX 0111 00001011 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vdiv_b LSX 0111 00001110 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vdiv_h LSX 0111 00001110 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vdiv_w LSX 0111 00001110 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vdiv_d LSX 0111 00001110 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vdiv_bu LSX 0111 00001110 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vdiv_hu LSX 0111 00001110 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vdiv_wu LSX 0111 00001110 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vdiv_du LSX 0111 00001110 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_b LSX 0111 00001110 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_h LSX 0111 00001110 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_w LSX 0111 00001110 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_d LSX 0111 00001110 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_bu LSX 0111 00001110 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_hu LSX 0111 00001110 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_wu LSX 0111 00001110 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmod_du LSX 0111 00001110 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsat_b LSX 0111 00110010 01000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsat_h LSX 0111 00110010 01000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsat_w LSX 0111 00110010 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsat_d LSX 0111 00110010 0101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsat_bu LSX 0111 00110010 10000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsat_hu LSX 0111 00110010 10000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsat_wu LSX 0111 00110010 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsat_du LSX 0111 00110010 1001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vexth_h_b LSX 0111 00101001 11101 11000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vexth_w_h LSX 0111 00101001 11101 11001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vexth_d_w LSX 0111 00101001 11101 11010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vexth_q_d LSX 0111 00101001 11101 11011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vexth_hu_bu LSX 0111 00101001 11101 11100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vexth_wu_hu LSX 0111 00101001 11101 11101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vexth_du_wu LSX 0111 00101001 11101 11110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vexth_qu_du LSX 0111 00101001 11101 11111 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsigncov_b LSX 0111 00010010 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsigncov_h LSX 0111 00010010 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsigncov_w LSX 0111 00010010 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsigncov_d LSX 0111 00010010 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vmskltz_b LSX 0111 00101001 11000 10000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmskltz_h LSX 0111 00101001 11000 10001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmskltz_w LSX 0111 00101001 11000 10010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmskltz_d LSX 0111 00101001 11000 10011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmskgez_b LSX 0111 00101001 11000 10100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vmsknz_b LSX 0111 00101001 11000 11000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vand_v LSX 0111 00010010 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vor_v LSX 0111 00010010 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vxor_v LSX 0111 00010010 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vnor_v LSX 0111 00010010 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vandn_v LSX 0111 00010010 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vorn_v LSX 0111 00010010 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vandi_b LSX 0111 00111101 00 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vori_b LSX 0111 00111101 01 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vxori_b LSX 0111 00111101 10 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vnori_b LSX 0111 00111101 11 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsll_b LSX 0111 00001110 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsll_h LSX 0111 00001110 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsll_w LSX 0111 00001110 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsll_d LSX 0111 00001110 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslli_b LSX 0111 00110010 11000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslli_h LSX 0111 00110010 11000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslli_w LSX 0111 00110010 11001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslli_d LSX 0111 00110010 1101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsrl_b LSX 0111 00001110 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrl_h LSX 0111 00001110 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrl_w LSX 0111 00001110 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrl_d LSX 0111 00001110 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrli_b LSX 0111 00110011 00000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrli_h LSX 0111 00110011 00000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrli_w LSX 0111 00110011 00001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrli_d LSX 0111 00110011 0001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsra_b LSX 0111 00001110 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsra_h LSX 0111 00001110 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsra_w LSX 0111 00001110 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsra_d LSX 0111 00001110 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrai_b LSX 0111 00110011 01000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrai_h LSX 0111 00110011 01000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrai_w LSX 0111 00110011 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrai_d LSX 0111 00110011 0101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vrotr_b LSX 0111 00001110 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vrotr_h LSX 0111 00001110 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vrotr_w LSX 0111 00001110 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vrotr_d LSX 0111 00001110 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vrotri_b LSX 0111 00101010 00000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vrotri_h LSX 0111 00101010 00000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vrotri_w LSX 0111 00101010 00001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vrotri_d LSX 0111 00101010 0001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsllwil_h_b LSX 0111 00110000 10000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsllwil_w_h LSX 0111 00110000 10000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsllwil_d_w LSX 0111 00110000 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vextl_q_d LSX 0111 00110000 10010 00000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsllwil_hu_bu LSX 0111 00110000 11000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsllwil_wu_hu LSX 0111 00110000 11000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsllwil_du_wu LSX 0111 00110000 11001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vextl_qu_du LSX 0111 00110000 11010 00000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsrlr_b LSX 0111 00001111 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlr_h LSX 0111 00001111 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlr_w LSX 0111 00001111 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlr_d LSX 0111 00001111 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlri_b LSX 0111 00101010 01000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlri_h LSX 0111 00101010 01000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlri_w LSX 0111 00101010 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlri_d LSX 0111 00101010 0101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsrar_b LSX 0111 00001111 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrar_h LSX 0111 00001111 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrar_w LSX 0111 00001111 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrar_d LSX 0111 00001111 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrari_b LSX 0111 00101010 10000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrari_h LSX 0111 00101010 10000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrari_w LSX 0111 00101010 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrari_d LSX 0111 00101010 1001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsrln_b_h LSX 0111 00001111 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrln_h_w LSX 0111 00001111 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrln_w_d LSX 0111 00001111 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsran_b_h LSX 0111 00001111 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsran_h_w LSX 0111 00001111 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsran_w_d LSX 0111 00001111 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsrlni_b_h LSX 0111 00110100 00000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlni_h_w LSX 0111 00110100 00001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlni_w_d LSX 0111 00110100 0001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlni_d_q LSX 0111 00110100 001 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrani_b_h LSX 0111 00110101 10000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrani_h_w LSX 0111 00110101 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrani_w_d LSX 0111 00110101 1001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrani_d_q LSX 0111 00110101 101 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsrlrn_b_h LSX 0111 00001111 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlrn_h_w LSX 0111 00001111 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlrn_w_d LSX 0111 00001111 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrarn_b_h LSX 0111 00001111 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrarn_h_w LSX 0111 00001111 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrarn_w_d LSX 0111 00001111 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsrlrni_b_h LSX 0111 00110100 01000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlrni_h_w LSX 0111 00110100 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlrni_w_d LSX 0111 00110100 0101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrlrni_d_q LSX 0111 00110100 011 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrarni_b_h LSX 0111 00110101 11000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrarni_h_w LSX 0111 00110101 11001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrarni_w_d LSX 0111 00110101 1101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsrarni_d_q LSX 0111 00110101 111 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vssrln_b_h LSX 0111 00001111 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrln_h_w LSX 0111 00001111 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrln_w_d LSX 0111 00001111 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssran_b_h LSX 0111 00001111 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssran_h_w LSX 0111 00001111 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssran_w_d LSX 0111 00001111 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrln_bu_h LSX 0111 00010000 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrln_hu_w LSX 0111 00010000 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrln_wu_d LSX 0111 00010000 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssran_bu_h LSX 0111 00010000 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssran_hu_w LSX 0111 00010000 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssran_wu_d LSX 0111 00010000 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vssrlni_b_h LSX 0111 00110100 10000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlni_h_w LSX 0111 00110100 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlni_w_d LSX 0111 00110100 1001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlni_d_q LSX 0111 00110100 101 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_b_h LSX 0111 00110110 00000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_h_w LSX 0111 00110110 00001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_w_d LSX 0111 00110110 0001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_d_q LSX 0111 00110110 001 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlni_bu_h LSX 0111 00110100 11000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlni_hu_w LSX 0111 00110100 11001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlni_wu_d LSX 0111 00110100 1101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlni_du_q LSX 0111 00110100 111 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_bu_h LSX 0111 00110110 01000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_hu_w LSX 0111 00110110 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_wu_d LSX 0111 00110110 0101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrani_du_q LSX 0111 00110110 011 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vssrlrn_b_h LSX 0111 00010000 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrn_h_w LSX 0111 00010000 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrn_w_d LSX 0111 00010000 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarn_b_h LSX 0111 00010000 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarn_h_w LSX 0111 00010000 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarn_w_d LSX 0111 00010000 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrn_bu_h LSX 0111 00010000 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrn_hu_w LSX 0111 00010000 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrn_wu_d LSX 0111 00010000 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarn_bu_h LSX 0111 00010000 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarn_hu_w LSX 0111 00010000 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarn_wu_d LSX 0111 00010000 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vssrlrni_b_h LSX 0111 00110101 00000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrni_h_w LSX 0111 00110101 00001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrni_w_d LSX 0111 00110101 0001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrni_d_q LSX 0111 00110101 001 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_b_h LSX 0111 00110110 10000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_h_w LSX 0111 00110110 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_w_d LSX 0111 00110110 1001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_d_q LSX 0111 00110110 101 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrni_hu_w LSX 0111 00110101 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrni_wu_d LSX 0111 00110101 0101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrlrni_du_q LSX 0111 00110101 011 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_bu_h LSX 0111 00110110 11000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_hu_w LSX 0111 00110110 11001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_wu_d LSX 0111 00110110 1101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vssrarni_du_q LSX 0111 00110110 111 imm:7 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vclo_b LSX 0111 00101001 11000 00000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vclo_h LSX 0111 00101001 11000 00001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vclo_w LSX 0111 00101001 11000 00010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vclo_d LSX 0111 00101001 11000 00011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vclz_b LSX 0111 00101001 11000 00100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vclz_h LSX 0111 00101001 11000 00101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vclz_w LSX 0111 00101001 11000 00110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vclz_d LSX 0111 00101001 11000 00111 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vpcnt_b LSX 0111 00101001 11000 01000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpcnt_h LSX 0111 00101001 11000 01001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpcnt_w LSX 0111 00101001 11000 01010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpcnt_d LSX 0111 00101001 11000 01011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vbitclr_b LSX 0111 00010000 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitclr_h LSX 0111 00010000 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitclr_w LSX 0111 00010000 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitclr_d LSX 0111 00010000 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitclri_b LSX 0111 00110001 00000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitclri_h LSX 0111 00110001 00000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitclri_w LSX 0111 00110001 00001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitclri_d LSX 0111 00110001 0001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitset_b LSX 0111 00010000 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitset_h LSX 0111 00010000 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitset_w LSX 0111 00010000 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitset_d LSX 0111 00010000 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitseti_b LSX 0111 00110001 01000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitseti_h LSX 0111 00110001 01000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitseti_w LSX 0111 00110001 01001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitseti_d LSX 0111 00110001 0101 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrev_b LSX 0111 00010001 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrev_h LSX 0111 00010001 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrev_w LSX 0111 00010001 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrev_d LSX 0111 00010001 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrevi_b LSX 0111 00110001 10000 01 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrevi_h LSX 0111 00110001 10000 1 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrevi_w LSX 0111 00110001 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbitrevi_d LSX 0111 00110001 1001 imm:6 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfrstp_b LSX 0111 00010010 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrstp_h LSX 0111 00010010 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrstpi_b LSX 0111 00101001 10100 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrstpi_h LSX 0111 00101001 10101 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfadd_s LSX 0111 00010011 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfadd_d LSX 0111 00010011 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfsub_s LSX 0111 00010011 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfsub_d LSX 0111 00010011 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmul_s LSX 0111 00010011 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmul_d LSX 0111 00010011 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfdiv_s LSX 0111 00010011 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfdiv_d LSX 0111 00010011 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfmadd_s LSX 0000 10010001 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmadd_d LSX 0000 10010010 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmsub_s LSX 0000 10010101 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmsub_d LSX 0000 10010110 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfnmadd_s LSX 0000 10011001 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfnmadd_d LSX 0000 10011010 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfnmsub_s LSX 0000 10011101 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfnmsub_d LSX 0000 10011110 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfmax_s LSX 0111 00010011 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmax_d LSX 0111 00010011 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmin_s LSX 0111 00010011 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmin_d LSX 0111 00010011 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfmaxa_s LSX 0111 00010100 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmaxa_d LSX 0111 00010100 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmina_s LSX 0111 00010100 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfmina_d LSX 0111 00010100 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vflogb_s LSX 0111 00101001 11001 10001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vflogb_d LSX 0111 00101001 11001 10010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfclass_s LSX 0111 00101001 11001 10101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfclass_d LSX 0111 00101001 11001 10110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfsqrt_s LSX 0111 00101001 11001 11001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfsqrt_d LSX 0111 00101001 11001 11010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrecip_s LSX 0111 00101001 11001 11101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrecip_d LSX 0111 00101001 11001 11110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrsqrt_s LSX 0111 00101001 11010 00001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrsqrt_d LSX 0111 00101001 11010 00010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfcvtl_s_h LSX 0111 00101001 11011 11010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfcvth_s_h LSX 0111 00101001 11011 11011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfcvtl_d_s LSX 0111 00101001 11011 11100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfcvth_d_s LSX 0111 00101001 11011 11101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfcvt_h_s LSX 0111 00010100 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfcvt_s_d LSX 0111 00010100 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vfrint_s LSX 0111 00101001 11010 01101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrint_d LSX 0111 00101001 11010 01110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrm_s LSX 0111 00101001 11010 10001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrm_d LSX 0111 00101001 11010 10010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrp_s LSX 0111 00101001 11010 10101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrp_d LSX 0111 00101001 11010 10110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrz_s LSX 0111 00101001 11010 11001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrz_d LSX 0111 00101001 11010 11010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrne_s LSX 0111 00101001 11010 11101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vfrintrne_d LSX 0111 00101001 11010 11110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vftint_w_s LSX 0111 00101001 11100 01100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftint_l_d LSX 0111 00101001 11100 01101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrm_w_s LSX 0111 00101001 11100 01110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrm_l_d LSX 0111 00101001 11100 01111 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrp_w_s LSX 0111 00101001 11100 10000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrp_l_d LSX 0111 00101001 11100 10001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrz_w_s LSX 0111 00101001 11100 10010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrz_l_d LSX 0111 00101001 11100 10011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrne_w_s LSX 0111 00101001 11100 10100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrne_l_d LSX 0111 00101001 11100 10101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftint_wu_s LSX 0111 00101001 11100 10110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftint_lu_d LSX 0111 00101001 11100 10111 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrz_wu_s LSX 0111 00101001 11100 11100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrz_lu_d LSX 0111 00101001 11100 11101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftint_w_d LSX 0111 00010100 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrm_w_d LSX 0111 00010100 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrp_w_d LSX 0111 00010100 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrz_w_d LSX 0111 00010100 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrne_w_d LSX 0111 00010100 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintl_l_s LSX 0111 00101001 11101 00000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftinth_l_s LSX 0111 00101001 11101 00001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrml_l_s LSX 0111 00101001 11101 00010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrmh_l_s LSX 0111 00101001 11101 00011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrpl_l_s LSX 0111 00101001 11101 00100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrph_l_s LSX 0111 00101001 11101 00101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrzl_l_s LSX 0111 00101001 11101 00110 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrzh_l_s LSX 0111 00101001 11101 00111 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrnel_l_s LSX 0111 00101001 11101 01000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vftintrneh_l_s LSX 0111 00101001 11101 01001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vffint_s_w LSX 0111 00101001 11100 00000 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vffint_s_wu LSX 0111 00101001 11100 00001 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vffint_d_l LSX 0111 00101001 11100 00010 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vffint_d_lu LSX 0111 00101001 11100 00011 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vffintl_d_w LSX 0111 00101001 11100 00100 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vffinth_d_w LSX 0111 00101001 11100 00101 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vffint_s_l LSX 0111 00010100 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vseq_b LSX 0111 00000000 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vseq_h LSX 0111 00000000 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vseq_w LSX 0111 00000000 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vseq_d LSX 0111 00000000 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vseqi_b LSX 0111 00101000 00000 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vseqi_h LSX 0111 00101000 00001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vseqi_w LSX 0111 00101000 00010 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vseqi_d LSX 0111 00101000 00011 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vsle_b LSX 0111 00000000 00100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsle_h LSX 0111 00000000 00101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsle_w LSX 0111 00000000 00110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsle_d LSX 0111 00000000 00111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_b LSX 0111 00101000 00100 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_h LSX 0111 00101000 00101 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_w LSX 0111 00101000 00110 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_d LSX 0111 00101000 00111 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsle_bu LSX 0111 00000000 01000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsle_hu LSX 0111 00000000 01001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsle_wu LSX 0111 00000000 01010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vsle_du LSX 0111 00000000 01011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_bu LSX 0111 00101000 01000 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_hu LSX 0111 00101000 01000 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_wu LSX 0111 00101000 01010 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslei_du LSX 0111 00101000 01010 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vslt_b LSX 0111 00000000 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslt_h LSX 0111 00000000 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslt_w LSX 0111 00000000 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslt_d LSX 0111 00000000 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_b LSX 0111 00101000 01100 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_h LSX 0111 00101000 01101 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_w LSX 0111 00101000 01110 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_d LSX 0111 00101000 01111 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslt_bu LSX 0111 00000000 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslt_hu LSX 0111 00000000 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslt_wu LSX 0111 00000000 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslt_du LSX 0111 00000000 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_bu LSX 0111 00101000 10000 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_hu LSX 0111 00101000 10001 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_wu LSX 0111 00101000 10010 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vslti_du LSX 0111 00101000 10011 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
vfcmp_cond_s LSX 0000 11000101 cond:5 vk:5 vj:5 vd:5 \
- !constraints { $cond > 0 && $cond < 0x12; }
+ !constraints { $cond > 0 && $cond < 0x12; } \
+ !clean { clean_lsx_result($vd); }
vfcmp_cond_d LSX 0000 11000110 cond:5 vk:5 vj:5 vd:5 \
- !constraints { $cond > 0 && $cond < 0x12; }
+ !constraints { $cond > 0 && $cond < 0x12; } \
+ !clean { clean_lsx_result($vd); }
-vbitsel_v LSX 0000 11010001 va:5 vk:5 vj:5 vd:5
+vbitsel_v LSX 0000 11010001 va:5 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
-vbitseli_b LSX 0111 00111100 01 imm:8 vj:5 vd:5
+vbitseli_b LSX 0111 00111100 01 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
vseteqz_v LSX 0111 00101001 11001 00110 vj:5 00 cd:3
vsetnez_v LSX 0111 00101001 11001 00111 vj:5 00 cd:3
@@ -1287,13 +1870,17 @@ vsetallnez_w LSX 0111 00101001 11001 01110 vj:5 00 cd:3
vsetallnez_d LSX 0111 00101001 11001 01111 vj:5 00 cd:3
vinsgr2vr_b LSX 0111 00101110 10111 0 imm:4 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vinsgr2vr_h LSX 0111 00101110 10111 10 imm:3 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vinsgr2vr_w LSX 0111 00101110 10111 110 imm:2 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vinsgr2vr_d LSX 0111 00101110 10111 1110 imm:1 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vpickve2gr_b LSX 0111 00101110 11111 0 imm:4 vj:5 rd:5 \
!constraints { $rd != 2 && $rd != 0; }
vpickve2gr_h LSX 0111 00101110 11111 10 imm:3 vj:5 rd:5 \
@@ -1312,111 +1899,171 @@ vpickve2gr_du LSX 0111 00101111 00111 1110 imm:1 vj:5 rd:5 \
!constraints { $rd != 2 && $rd != 0; }
vreplgr2vr_b LSX 0111 00101001 11110 00000 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vreplgr2vr_h LSX 0111 00101001 11110 00001 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vreplgr2vr_w LSX 0111 00101001 11110 00010 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vreplgr2vr_d LSX 0111 00101001 11110 00011 rj:5 vd:5 \
- !constraints { $rj != 2 && $rj != 0; }
+ !constraints { $rj != 2 && $rj != 0; } \
+ !clean { clean_lsx_result($vd); }
vreplve_b LSX 0111 00010010 00100 rk:5 vj:5 vd:5 \
- !constraints { $rk != 2 && $rk != 0; }
+ !constraints { $rk != 2 && $rk != 0; } \
+ !clean { clean_lsx_result($vd); }
vreplve_h LSX 0111 00010010 00101 rk:5 vj:5 vd:5 \
- !constraints { $rk != 2 && $rk != 0; }
+ !constraints { $rk != 2 && $rk != 0; } \
+ !clean { clean_lsx_result($vd); }
vreplve_w LSX 0111 00010010 00110 rk:5 vj:5 vd:5 \
- !constraints { $rk != 2 && $rk != 0; }
+ !constraints { $rk != 2 && $rk != 0; } \
+ !clean { clean_lsx_result($vd); }
vreplve_d LSX 0111 00010010 00111 rk:5 vj:5 vd:5 \
- !constraints { $rk != 2 && $rk != 0; }
-
-vreplvei_b LSX 0111 00101111 01111 0 imm:4 vj:5 vd:5
-vreplvei_h LSX 0111 00101111 01111 10 imm:3 vj:5 vd:5
-vreplvei_w LSX 0111 00101111 01111 110 imm:2 vj:5 vd:5
-vreplvei_d LSX 0111 00101111 01111 1110 imm:1 vj:5 vd:5
-
-vbsll_v LSX 0111 00101000 11100 imm:5 vj:5 vd:5
-vbsrl_v LSX 0111 00101000 11101 imm:5 vj:5 vd:5
-
-vpackev_b LSX 0111 00010001 01100 vk:5 vj:5 vd:5
-vpackev_h LSX 0111 00010001 01101 vk:5 vj:5 vd:5
-vpackev_w LSX 0111 00010001 01110 vk:5 vj:5 vd:5
-vpackev_d LSX 0111 00010001 01111 vk:5 vj:5 vd:5
-vpackod_b LSX 0111 00010001 10000 vk:5 vj:5 vd:5
-vpackod_h LSX 0111 00010001 10001 vk:5 vj:5 vd:5
-vpackod_w LSX 0111 00010001 10010 vk:5 vj:5 vd:5
-vpackod_d LSX 0111 00010001 10011 vk:5 vj:5 vd:5
-
-vpickev_b LSX 0111 00010001 11100 vk:5 vj:5 vd:5
-vpickev_h LSX 0111 00010001 11101 vk:5 vj:5 vd:5
-vpickev_w LSX 0111 00010001 11110 vk:5 vj:5 vd:5
-vpickev_d LSX 0111 00010001 11111 vk:5 vj:5 vd:5
-vpickod_b LSX 0111 00010010 00000 vk:5 vj:5 vd:5
-vpickod_h LSX 0111 00010010 00001 vk:5 vj:5 vd:5
-vpickod_w LSX 0111 00010010 00010 vk:5 vj:5 vd:5
-vpickod_d LSX 0111 00010010 00011 vk:5 vj:5 vd:5
-
-vilvl_b LSX 0111 00010001 10100 vk:5 vj:5 vd:5
-vilvl_h LSX 0111 00010001 10101 vk:5 vj:5 vd:5
-vilvl_w LSX 0111 00010001 10110 vk:5 vj:5 vd:5
-vilvl_d LSX 0111 00010001 10111 vk:5 vj:5 vd:5
-vilvh_b LSX 0111 00010001 11000 vk:5 vj:5 vd:5
-vilvh_h LSX 0111 00010001 11001 vk:5 vj:5 vd:5
-vilvh_w LSX 0111 00010001 11010 vk:5 vj:5 vd:5
-vilvh_d LSX 0111 00010001 11011 vk:5 vj:5 vd:5
-
-vshuf4i_b LSX 0111 00111001 00 imm:8 vj:5 vd:5
-vshuf4i_h LSX 0111 00111001 01 imm:8 vj:5 vd:5
-vshuf4i_w LSX 0111 00111001 10 imm:8 vj:5 vd:5
-vshuf4i_d LSX 0111 00111001 11 imm:8 vj:5 vd:5
-
-vpermi_w LSX 0111 00111110 01 imm:8 vj:5 vd:5
-
-vextrins_d LSX 0111 00111000 00 imm:8 vj:5 vd:5
-vextrins_w LSX 0111 00111000 01 imm:8 vj:5 vd:5
-vextrins_h LSX 0111 00111000 10 imm:8 vj:5 vd:5
-vextrins_b LSX 0111 00111000 11 imm:8 vj:5 vd:5
+ !constraints { $rk != 2 && $rk != 0; } \
+ !clean { clean_lsx_result($vd); }
+
+vreplvei_b LSX 0111 00101111 01111 0 imm:4 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vreplvei_h LSX 0111 00101111 01111 10 imm:3 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vreplvei_w LSX 0111 00101111 01111 110 imm:2 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vreplvei_d LSX 0111 00101111 01111 1110 imm:1 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vbsll_v LSX 0111 00101000 11100 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vbsrl_v LSX 0111 00101000 11101 imm:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vpackev_b LSX 0111 00010001 01100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpackev_h LSX 0111 00010001 01101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpackev_w LSX 0111 00010001 01110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpackev_d LSX 0111 00010001 01111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpackod_b LSX 0111 00010001 10000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpackod_h LSX 0111 00010001 10001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpackod_w LSX 0111 00010001 10010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpackod_d LSX 0111 00010001 10011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vpickev_b LSX 0111 00010001 11100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpickev_h LSX 0111 00010001 11101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpickev_w LSX 0111 00010001 11110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpickev_d LSX 0111 00010001 11111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpickod_b LSX 0111 00010010 00000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpickod_h LSX 0111 00010010 00001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpickod_w LSX 0111 00010010 00010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vpickod_d LSX 0111 00010010 00011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vilvl_b LSX 0111 00010001 10100 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vilvl_h LSX 0111 00010001 10101 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vilvl_w LSX 0111 00010001 10110 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vilvl_d LSX 0111 00010001 10111 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vilvh_b LSX 0111 00010001 11000 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vilvh_h LSX 0111 00010001 11001 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vilvh_w LSX 0111 00010001 11010 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vilvh_d LSX 0111 00010001 11011 vk:5 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vshuf4i_b LSX 0111 00111001 00 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vshuf4i_h LSX 0111 00111001 01 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vshuf4i_w LSX 0111 00111001 10 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vshuf4i_d LSX 0111 00111001 11 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vpermi_w LSX 0111 00111110 01 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+
+vextrins_d LSX 0111 00111000 00 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vextrins_w LSX 0111 00111000 01 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vextrins_h LSX 0111 00111000 10 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
+vextrins_b LSX 0111 00111000 11 imm:8 vj:5 vd:5 \
+ !clean { clean_lsx_result($vd); }
vld LSX 0010 110000 si12:12 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); } \
+ !clean { clean_lsx_result($vd); }
vst LSX 0010 110001 si12:12 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); } \
+ !clean { clean_lsx_result($vd); }
vldx LSX 0011 10000100 00000 rk:5 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != $rk && $rk != 2 && $rj != 2; } \
- !memory { reg_plus_reg($rj, $rk); }
+ !memory { reg_plus_reg($rj, $rk); } \
+ !clean { clean_lsx_result($vd); }
vstx LSX 0011 10000100 01000 rk:5 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != $rk && $rk != 2 && $rj != 2; } \
- !memory { reg_plus_reg($rj, $rk); }
+ !memory { reg_plus_reg($rj, $rk); } \
+ !clean { clean_lsx_result($vd); }
vldrepl_d LSX 0011 00000001 0 si9:9 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si9, 9) * 8); }
+ !memory { reg_plus_imm($rj, sextract($si9, 9) * 8); } \
+ !clean { clean_lsx_result($vd); }
vldrepl_w LSX 0011 00000010 si10:10 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si10, 10) * 4); }
+ !memory { reg_plus_imm($rj, sextract($si10, 10) * 4); } \
+ !clean { clean_lsx_result($vd); }
vldrepl_h LSX 0011 0000010 si11:11 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si11, 11) * 2); }
+ !memory { reg_plus_imm($rj, sextract($si11, 11) * 2); } \
+ !clean { clean_lsx_result($vd); }
vldrepl_b LSX 0011 000010 si12:12 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si12, 12)); }
+ !memory { reg_plus_imm($rj, sextract($si12, 12)); } \
+ !clean { clean_lsx_result($vd); }
vstelm_d LSX 0011 00010001 0 si1:1 si8:8 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si8, 8) * 8); }
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 8); } \
+ !clean { clean_lsx_result($vd); }
vstelm_w LSX 0011 00010010 si2:2 si8:8 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si8, 8) * 4); }
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 4); } \
+ !clean { clean_lsx_result($vd); }
vstelm_h LSX 0011 0001010 si3:3 si8:8 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si8, 8) * 2); }
+ !memory { reg_plus_imm($rj, sextract($si8, 8) * 2); } \
+ !clean { clean_lsx_result($vd); }
vstelm_b LSX 0011 000110 si4:4 si8:8 rj:5 vd:5 \
!constraints { $rj != 0 && $rj != 2; } \
- !memory { reg_plus_imm($rj, sextract($si8, 8)); }
+ !memory { reg_plus_imm($rj, sextract($si8, 8)); } \
+ !clean { clean_lsx_result($vd); }
vldi LSX 0111 00111110 00 si13:13 vd:5 \
- !constraints { $si13 >= 0 && $si13 <= 12; }
+ !constraints { $si13 >= 0 && $si13 <= 12; } \
+ !clean { clean_lsx_result($vd); }
#
# LASX instructions
diff --git a/risugen b/risugen
index fa94a39..8a67fdf 100755
--- a/risugen
+++ b/risugen
@@ -43,7 +43,7 @@ my @pattern_re = (); # include pattern
my @not_pattern_re = (); # exclude pattern
# Valid block names (keys in blocks hash)
-my %valid_blockname = ( constraints => 1, memory => 1, safefloat =>1 );
+my %valid_blockname = ( constraints => 1, memory => 1, safefloat =>1, clean => 1 );
sub parse_risu_directive($$@)
{
diff --git a/risugen_loongarch64.pm b/risugen_loongarch64.pm
index b3f901d..97f00f3 100644
--- a/risugen_loongarch64.pm
+++ b/risugen_loongarch64.pm
@@ -81,6 +81,18 @@ sub nanbox_s($)
return $fpreg;
}
+sub clean_lsx_result($)
+{
+ my ($vreg) = @_;
+
+ # xvinsgr2vr.d vd, r0, 2;
+ insn32(0x76ebe000 | 2 << 10 | $vreg);
+ # xvinsgr2vr.d vd, r0, 3;
+ insn32(0x76ebe000 | 3 << 10 | $vreg);
+
+ return $vreg;
+}
+
sub align($)
{
my ($a) = @_;
@@ -405,6 +417,7 @@ sub gen_one_insn($$)
my $constraint = $rec->{blocks}{"constraints"};
my $memblock = $rec->{blocks}{"memory"};
my $safefloat = $rec->{blocks}{"safefloat"};
+ my $clean = $rec->{blocks}{"clean"};
$insn &= ~$fixedbitmask;
$insn |= $fixedbits;
@@ -448,6 +461,13 @@ sub gen_one_insn($$)
$resultreg = eval_with_fields($insnname, $insn, $rec, "safefloat", $safefloat);
}
+ if (defined $clean) {
+ # LSX insns only care about low 128 bit,
+ # so we use clean_lsx_result() make sure that high 128bit is 0x0;
+ my $cleanreg;
+ $cleanreg = eval_with_fields($insnname, $insn, $rec, "clean", $clean);
+ }
+
if (defined $memblock) {
# Clean up following a memory access instruction:
# we need to turn the (possibly written-back) basereg
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [risu PATCH 5/5] loongarch: Add block 'clean' and clean_lsx_result()
2023-10-25 9:29 ` [risu PATCH 5/5] loongarch: Add block 'clean' and clean_lsx_result() Song Gao
@ 2023-12-12 12:39 ` Peter Maydell
2023-12-13 1:30 ` gaosong
0 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2023-12-12 12:39 UTC (permalink / raw)
To: Song Gao; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
On Wed, 25 Oct 2023 at 10:29, Song Gao <gaosong@loongson.cn> wrote:
>
> The result of the LSX instruction is in the low 128 bits
> of the vreg register. We use clean_lsx_result() to clean up
> the high 128 bits of the vreg register.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> loongarch64.risu | 2121 ++++++++++++++++++++++++++--------------
> risugen | 2 +-
> risugen_loongarch64.pm | 20 +
> 3 files changed, 1405 insertions(+), 738 deletions(-)
>
> diff --git a/loongarch64.risu b/loongarch64.risu
> index 596de90..531470d 100644
> --- a/loongarch64.risu
> +++ b/loongarch64.risu
> @@ -64,26 +64,26 @@ mulw_d_wu LA64 0000 00000001 11111 rk:5 rj:5 rd:5 \
> #div.{w[u]/d[u]} rd,rj,rk
> # div.w{u}, mod.w[u] rk, rj, need in [0x0 ~0x7FFFFFFF]
> # use function set_reg_w($reg)
> -div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> - !memory { set_reg_w($rj); set_reg_w($rk); }
> -div_wu LA64 0000 00000010 00010 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> - !memory { set_reg_w($rj); set_reg_w($rk); }
> -div_d LA64 0000 00000010 00100 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> -div_du LA64 0000 00000010 00110 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> -mod_w LA64 0000 00000010 00001 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> - !memory { set_reg_w($rj); set_reg_w($rk); }
> -mod_wu LA64 0000 00000010 00011 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> - !memory { set_reg_w($rj); set_reg_w($rk); }
> -mod_d LA64 0000 00000010 00101 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> -mod_du LA64 0000 00000010 00111 rk:5 rj:5 rd:5 \
> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> +#div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> +# !memory { set_reg_w($rj); set_reg_w($rk); }
> +#div_wu LA64 0000 00000010 00010 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> +# !memory { set_reg_w($rj); set_reg_w($rk); }
> +#div_d LA64 0000 00000010 00100 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> +#div_du LA64 0000 00000010 00110 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> +#mod_w LA64 0000 00000010 00001 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> +# !memory { set_reg_w($rj); set_reg_w($rk); }
> +#mod_wu LA64 0000 00000010 00011 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
> +# !memory { set_reg_w($rj); set_reg_w($rk); }
> +#mod_d LA64 0000 00000010 00101 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> +#mod_du LA64 0000 00000010 00111 rk:5 rj:5 rd:5 \
> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
Why do we comment out all these patterns ? The commit
message doesn't say anything about this.
>
> alsl_w LA64 0000 00000000 010 sa2:2 rk:5 rj:5 rd:5 \
> !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> @@ -615,665 +615,1248 @@ fstx_d LA64 0011 10000011 11000 rk:5 rj:5 fd:5 \
> # LSX instructions
> #
>
> -vadd_b LSX 0111 00000000 10100 vk:5 vj:5 vd:5
> -vadd_h LSX 0111 00000000 10101 vk:5 vj:5 vd:5
> +vadd_b LSX 0111 00000000 10100 vk:5 vj:5 vd:5 \
> + !clean { clean_lsx_result($vd); }
> +vadd_h LSX 0111 00000000 10101 vk:5 vj:5 vd:5 \
> + !clean { clean_lsx_result($vd); }
If there are patterns that need the clean_lsx_result
handling, then add the support for that first, rather
than adding a broken pattern and then editing it to
add the extra block to every pattern, please.
> diff --git a/risugen b/risugen
> index fa94a39..8a67fdf 100755
> --- a/risugen
> +++ b/risugen
> @@ -43,7 +43,7 @@ my @pattern_re = (); # include pattern
> my @not_pattern_re = (); # exclude pattern
>
> # Valid block names (keys in blocks hash)
> -my %valid_blockname = ( constraints => 1, memory => 1, safefloat =>1 );
> +my %valid_blockname = ( constraints => 1, memory => 1, safefloat =>1, clean => 1 );
>
> sub parse_risu_directive($$@)
> {
> diff --git a/risugen_loongarch64.pm b/risugen_loongarch64.pm
> index b3f901d..97f00f3 100644
> --- a/risugen_loongarch64.pm
> +++ b/risugen_loongarch64.pm
> @@ -81,6 +81,18 @@ sub nanbox_s($)
> return $fpreg;
> }
>
> +sub clean_lsx_result($)
> +{
> + my ($vreg) = @_;
> +
> + # xvinsgr2vr.d vd, r0, 2;
> + insn32(0x76ebe000 | 2 << 10 | $vreg);
> + # xvinsgr2vr.d vd, r0, 3;
> + insn32(0x76ebe000 | 3 << 10 | $vreg);
> +
> + return $vreg;
> +}
> +
> sub align($)
> {
> my ($a) = @_;
> @@ -405,6 +417,7 @@ sub gen_one_insn($$)
> my $constraint = $rec->{blocks}{"constraints"};
> my $memblock = $rec->{blocks}{"memory"};
> my $safefloat = $rec->{blocks}{"safefloat"};
> + my $clean = $rec->{blocks}{"clean"};
>
> $insn &= ~$fixedbitmask;
> $insn |= $fixedbits;
> @@ -448,6 +461,13 @@ sub gen_one_insn($$)
> $resultreg = eval_with_fields($insnname, $insn, $rec, "safefloat", $safefloat);
> }
>
> + if (defined $clean) {
> + # LSX insns only care about low 128 bit,
> + # so we use clean_lsx_result() make sure that high 128bit is 0x0;
> + my $cleanreg;
> + $cleanreg = eval_with_fields($insnname, $insn, $rec, "clean", $clean);
> + }
> +
> if (defined $memblock) {
> # Clean up following a memory access instruction:
> # we need to turn the (possibly written-back) basereg
> --
The handling here is exactly identical to the existing "safefloat"
block, and 'safefloat' does nothing floating point specific and
the new 'clean' block does nothing LSX specific. I think we would
do better to have a single block type for "do anything you need to
do to clean up after the insn", and use it for both the patterns
that need to tidy up a float register and those that need to do
this new LSX related tidying.
Open to suggestions for better naming, but my suggestion is that
we call this block type "!post" (because it is the hook for
doing things after emitting the instruction). In future if
we ever needed it we could add a "!pre".
That is:
* rename "!safefloat" to "!post"
* add the clean_lsx_result() function before adding the LSX
etc patterns, so we don't need to add the patterns and then
change them later to add a "!post" block
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [risu PATCH 5/5] loongarch: Add block 'clean' and clean_lsx_result()
2023-12-12 12:39 ` Peter Maydell
@ 2023-12-13 1:30 ` gaosong
0 siblings, 0 replies; 11+ messages in thread
From: gaosong @ 2023-12-13 1:30 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
在 2023/12/12 下午8:39, Peter Maydell 写道:
> On Wed, 25 Oct 2023 at 10:29, Song Gao<gaosong@loongson.cn> wrote:
>> The result of the LSX instruction is in the low 128 bits
>> of the vreg register. We use clean_lsx_result() to clean up
>> the high 128 bits of the vreg register.
>>
>> Signed-off-by: Song Gao<gaosong@loongson.cn>
>> ---
>> loongarch64.risu | 2121 ++++++++++++++++++++++++++--------------
>> risugen | 2 +-
>> risugen_loongarch64.pm | 20 +
>> 3 files changed, 1405 insertions(+), 738 deletions(-)
>>
>> diff --git a/loongarch64.risu b/loongarch64.risu
>> index 596de90..531470d 100644
>> --- a/loongarch64.risu
>> +++ b/loongarch64.risu
>> @@ -64,26 +64,26 @@ mulw_d_wu LA64 0000 00000001 11111 rk:5 rj:5 rd:5 \
>> #div.{w[u]/d[u]} rd,rj,rk
>> # div.w{u}, mod.w[u] rk, rj, need in [0x0 ~0x7FFFFFFF]
>> # use function set_reg_w($reg)
>> -div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> - !memory { set_reg_w($rj); set_reg_w($rk); }
>> -div_wu LA64 0000 00000010 00010 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> - !memory { set_reg_w($rj); set_reg_w($rk); }
>> -div_d LA64 0000 00000010 00100 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> -div_du LA64 0000 00000010 00110 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> -mod_w LA64 0000 00000010 00001 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> - !memory { set_reg_w($rj); set_reg_w($rk); }
>> -mod_wu LA64 0000 00000010 00011 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> - !memory { set_reg_w($rj); set_reg_w($rk); }
>> -mod_d LA64 0000 00000010 00101 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> -mod_du LA64 0000 00000010 00111 rk:5 rj:5 rd:5 \
>> - !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> +#div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> +# !memory { set_reg_w($rj); set_reg_w($rk); }
>> +#div_wu LA64 0000 00000010 00010 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> +# !memory { set_reg_w($rj); set_reg_w($rk); }
>> +#div_d LA64 0000 00000010 00100 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> +#div_du LA64 0000 00000010 00110 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> +#mod_w LA64 0000 00000010 00001 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> +# !memory { set_reg_w($rj); set_reg_w($rk); }
>> +#mod_wu LA64 0000 00000010 00011 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; } \
>> +# !memory { set_reg_w($rj); set_reg_w($rk); }
>> +#mod_d LA64 0000 00000010 00101 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> +#mod_du LA64 0000 00000010 00111 rk:5 rj:5 rd:5 \
>> +# !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
> Why do we comment out all these patterns ? The commit
> message doesn't say anything about this.
>
I will drop them.
These instructions, test need patch[1], but the patch is't merged.
[1] :
https://lore.kernel.org/all/3c401d0f-a34f-bd29-03a3-dddfae94ce0a@loongson.cn/#r
>> alsl_w LA64 0000 00000000 010 sa2:2 rk:5 rj:5 rd:5 \
>> !constraints { $rk != 2 && $rj != 2 && $rd != 2; }
>> @@ -615,665 +615,1248 @@ fstx_d LA64 0011 10000011 11000 rk:5 rj:5 fd:5 \
>> # LSX instructions
>> #
>>
>> -vadd_b LSX 0111 00000000 10100 vk:5 vj:5 vd:5
>> -vadd_h LSX 0111 00000000 10101 vk:5 vj:5 vd:5
>> +vadd_b LSX 0111 00000000 10100 vk:5 vj:5 vd:5 \
>> + !clean { clean_lsx_result($vd); }
>> +vadd_h LSX 0111 00000000 10101 vk:5 vj:5 vd:5 \
>> + !clean { clean_lsx_result($vd); }
> If there are patterns that need the clean_lsx_result
> handling, then add the support for that first, rather
> than adding a broken pattern and then editing it to
> add the extra block to every pattern, please.
Got it.
>> diff --git a/risugen b/risugen
>> index fa94a39..8a67fdf 100755
>> --- a/risugen
>> +++ b/risugen
>> @@ -43,7 +43,7 @@ my @pattern_re = (); # include pattern
>> my @not_pattern_re = (); # exclude pattern
>>
>> # Valid block names (keys in blocks hash)
>> -my %valid_blockname = ( constraints => 1, memory => 1, safefloat =>1 );
>> +my %valid_blockname = ( constraints => 1, memory => 1, safefloat =>1, clean => 1 );
>>
>> sub parse_risu_directive($$@)
>> {
>> diff --git a/risugen_loongarch64.pm b/risugen_loongarch64.pm
>> index b3f901d..97f00f3 100644
>> --- a/risugen_loongarch64.pm
>> +++ b/risugen_loongarch64.pm
>> @@ -81,6 +81,18 @@ sub nanbox_s($)
>> return $fpreg;
>> }
>>
>> +sub clean_lsx_result($)
>> +{
>> + my ($vreg) = @_;
>> +
>> + # xvinsgr2vr.d vd, r0, 2;
>> + insn32(0x76ebe000 | 2 << 10 | $vreg);
>> + # xvinsgr2vr.d vd, r0, 3;
>> + insn32(0x76ebe000 | 3 << 10 | $vreg);
>> +
>> + return $vreg;
>> +}
>> +
>> sub align($)
>> {
>> my ($a) = @_;
>> @@ -405,6 +417,7 @@ sub gen_one_insn($$)
>> my $constraint = $rec->{blocks}{"constraints"};
>> my $memblock = $rec->{blocks}{"memory"};
>> my $safefloat = $rec->{blocks}{"safefloat"};
>> + my $clean = $rec->{blocks}{"clean"};
>>
>> $insn &= ~$fixedbitmask;
>> $insn |= $fixedbits;
>> @@ -448,6 +461,13 @@ sub gen_one_insn($$)
>> $resultreg = eval_with_fields($insnname, $insn, $rec, "safefloat", $safefloat);
>> }
>>
>> + if (defined $clean) {
>> + # LSX insns only care about low 128 bit,
>> + # so we use clean_lsx_result() make sure that high 128bit is 0x0;
>> + my $cleanreg;
>> + $cleanreg = eval_with_fields($insnname, $insn, $rec, "clean", $clean);
>> + }
>> +
>> if (defined $memblock) {
>> # Clean up following a memory access instruction:
>> # we need to turn the (possibly written-back) basereg
>> --
> The handling here is exactly identical to the existing "safefloat"
> block, and 'safefloat' does nothing floating point specific and
> the new 'clean' block does nothing LSX specific. I think we would
> do better to have a single block type for "do anything you need to
> do to clean up after the insn", and use it for both the patterns
> that need to tidy up a float register and those that need to do
> this new LSX related tidying.
>
> Open to suggestions for better naming, but my suggestion is that
> we call this block type "!post" (because it is the hook for
> doing things after emitting the instruction). In future if
> we ever needed it we could add a "!pre".
>
> That is:
> * rename "!safefloat" to "!post"
> * add the clean_lsx_result() function before adding the LSX
> etc patterns, so we don't need to add the patterns and then
> change them later to add a "!post" block
>
> thanks
> -- PMM
Thanks for your suggestions and review!
I'll send v2 soon,
Thanks.
Song Gao.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [risu PATCH 0/5] Add LoongArch LSX/LASX instructions
2023-10-25 9:29 [risu PATCH 0/5] Add LoongArch LSX/LASX instructions Song Gao
` (4 preceding siblings ...)
2023-10-25 9:29 ` [risu PATCH 5/5] loongarch: Add block 'clean' and clean_lsx_result() Song Gao
@ 2023-11-13 8:06 ` gaosong
2023-11-24 8:26 ` gaosong
5 siblings, 1 reply; 11+ messages in thread
From: gaosong @ 2023-11-13 8:06 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
Ping !
在 2023/10/25 下午5:29, Song Gao 写道:
> Hi, Peter!
>
> This series adds LSX/LASX instructions.
>
> We tested 10 million instructions without any problems.
>
> client:
> x86 host QEMU + patches [1].
>
> server:
> 3A5000 host.
>
>
> [1] https://patchwork.kernel.org/project/qemu-devel/list/?series=791633
>
>
> Please review!
>
> Thanks.
> Song Gao
>
> Song Gao (5):
> loongarch: Add LSX instructions
> loongarch: Add LASX instructions
> loongarch: reginfo suport LSX/LASX
> loongarch: init LASX registers
> loongarch: Add block 'clean' and clean_lsx_result()
>
> loongarch64.risu | 2309 +++++++++++++++++++++++++++++++++++-
> risu_reginfo_loongarch64.c | 107 +-
> risu_reginfo_loongarch64.h | 3 +-
> risugen | 2 +-
> risugen_loongarch64.pm | 30 +
> 5 files changed, 2418 insertions(+), 33 deletions(-)
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [risu PATCH 0/5] Add LoongArch LSX/LASX instructions
2023-11-13 8:06 ` [risu PATCH 0/5] Add LoongArch LSX/LASX instructions gaosong
@ 2023-11-24 8:26 ` gaosong
2023-12-12 12:40 ` Peter Maydell
0 siblings, 1 reply; 11+ messages in thread
From: gaosong @ 2023-11-24 8:26 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
Ping !!
Since [1] series had merged into master three weeks ago,
I ping this series again.
[1]:
https://lore.kernel.org/all/20231103062332.2413724-1-gaosong@loongson.cn/
Thanks.
Song Gao
在 2023/11/13 下午4:06, gaosong 写道:
> Ping !
>
> 在 2023/10/25 下午5:29, Song Gao 写道:
>> Hi, Peter!
>>
>> This series adds LSX/LASX instructions.
>>
>> We tested 10 million instructions without any problems.
>>
>> client:
>> x86 host QEMU + patches [1].
>>
>> server:
>> 3A5000 host.
>>
>>
>> [1] https://patchwork.kernel.org/project/qemu-devel/list/?series=791633
>>
>>
>> Please review!
>>
>> Thanks.
>> Song Gao
>>
>> Song Gao (5):
>> loongarch: Add LSX instructions
>> loongarch: Add LASX instructions
>> loongarch: reginfo suport LSX/LASX
>> loongarch: init LASX registers
>> loongarch: Add block 'clean' and clean_lsx_result()
>>
>> loongarch64.risu | 2309 +++++++++++++++++++++++++++++++++++-
>> risu_reginfo_loongarch64.c | 107 +-
>> risu_reginfo_loongarch64.h | 3 +-
>> risugen | 2 +-
>> risugen_loongarch64.pm | 30 +
>> 5 files changed, 2418 insertions(+), 33 deletions(-)
>>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [risu PATCH 0/5] Add LoongArch LSX/LASX instructions
2023-11-24 8:26 ` gaosong
@ 2023-12-12 12:40 ` Peter Maydell
0 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2023-12-12 12:40 UTC (permalink / raw)
To: gaosong; +Cc: qemu-devel, richard.henderson, philmd, alex.bennee, maobibo
On Fri, 24 Nov 2023 at 08:26, gaosong <gaosong@loongson.cn> wrote:
>
> Ping !!
>
> Since [1] series had merged into master three weeks ago,
>
> I ping this series again.
Apologies for taking so long with this, I think I
lost track of it and then we've had the release period.
I have no particular issues with the first four
patches, and have left some review comments on the
last one.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread