From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL v2 00/14] RISC-V Patch Queue for 5.1
Date: Thu, 30 Apr 2020 12:52:33 +0100 [thread overview]
Message-ID: <CAFEAcA8d5y1d0hsNfPakVxoTqdPJ7NSUr6d5PQcwRDUtX9pq4A@mail.gmail.com> (raw)
In-Reply-To: <20200429202006.775322-1-alistair.francis@wdc.com>
On Wed, 29 Apr 2020 at 21:28, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200429-2
>
> for you to fetch changes up to 31e6d70485b1a719ca27e9a2d21f2a61ac497cdf:
>
> hw/riscv/spike: Allow more than one CPUs (2020-04-29 13:16:38 -0700)
>
> ----------------------------------------------------------------
> RISC-V pull request for 5.1
>
> This is the first pull request for the 5.1 development period. It
> contains all of the patches that were sent during the 5.0 timeframe.
>
> This is an assortment of fixes for RISC-V, including fixes for the
> Hypervisor extension, the Spike machine and an update to OpenSBI.
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
prev parent reply other threads:[~2020-04-30 12:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-29 20:19 [PULL v2 00/14] RISC-V Patch Queue for 5.1 Alistair Francis
2020-04-29 20:19 ` [PULL v2 01/14] riscv/sifive_u: Fix up file ordering Alistair Francis
2020-04-29 20:19 ` [PULL v2 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC Alistair Francis
2020-04-29 20:19 ` [PULL v2 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine Alistair Francis
2020-04-29 20:19 ` [PULL v2 04/14] riscv: Don't use stage-2 PTE lookup protection flags Alistair Francis
2020-04-29 20:19 ` [PULL v2 05/14] riscv: AND stage-1 and stage-2 " Alistair Francis
2020-04-29 20:19 ` [PULL v2 06/14] riscv: Fix Stage2 SV32 page table walk Alistair Francis
2020-04-29 20:19 ` [PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines Alistair Francis
2020-04-29 20:20 ` [PULL v2 08/14] riscv: sifive_e: Support changing CPU type Alistair Francis
2020-04-29 20:20 ` [PULL v2 09/14] target/riscv: Add a sifive-e34 cpu type Alistair Francis
2020-04-29 20:20 ` [PULL v2 10/14] linux-user/riscv: fix up struct target_ucontext definition Alistair Francis
2020-04-29 20:20 ` [PULL v2 11/14] roms: opensbi: Upgrade from v0.6 to v0.7 Alistair Francis
2020-04-29 20:20 ` [PULL v2 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() Alistair Francis
2020-04-29 20:20 ` [PULL v2 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option Alistair Francis
2020-04-29 20:20 ` [PULL v2 14/14] hw/riscv/spike: Allow more than one CPUs Alistair Francis
2020-04-30 11:52 ` Peter Maydell [this message]
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