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* [PULL v2 00/14] RISC-V Patch Queue for 5.1
@ 2020-04-29 20:19 Alistair Francis
  2020-04-29 20:19 ` [PULL v2 01/14] riscv/sifive_u: Fix up file ordering Alistair Francis
                   ` (14 more replies)
  0 siblings, 15 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-29 20:19 UTC (permalink / raw)
  To: peter.maydell; +Cc: Alistair Francis, palmerdabbelt, qemu-riscv, qemu-devel

The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200429-2

for you to fetch changes up to 31e6d70485b1a719ca27e9a2d21f2a61ac497cdf:

  hw/riscv/spike: Allow more than one CPUs (2020-04-29 13:16:38 -0700)

----------------------------------------------------------------
RISC-V pull request for 5.1

This is the first pull request for the 5.1 development period. It
contains all of the patches that were sent during the 5.0 timeframe.

This is an assortment of fixes for RISC-V, including fixes for the
Hypervisor extension, the Spike machine and an update to OpenSBI.

----------------------------------------------------------------
Alistair Francis (4):
      riscv/sifive_u: Fix up file ordering
      riscv/sifive_u: Add a serial property to the sifive_u SoC
      riscv: Don't use stage-2 PTE lookup protection flags
      riscv: AND stage-1 and stage-2 protection flags

Anup Patel (4):
      riscv: Fix Stage2 SV32 page table walk
      hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
      hw/riscv/spike: Allow loading firmware separately using -bios option
      hw/riscv/spike: Allow more than one CPUs

Bin Meng (3):
      riscv/sifive_u: Add a serial property to the sifive_u machine
      hw/riscv: Generate correct "mmu-type" for 32-bit machines
      roms: opensbi: Upgrade from v0.6 to v0.7

Corey Wharton (2):
      riscv: sifive_e: Support changing CPU type
      target/riscv: Add a sifive-e34 cpu type

LIU Zhiwei (1):
      linux-user/riscv: fix up struct target_ucontext definition

 hw/riscv/boot.c                              |  13 ++-
 hw/riscv/sifive_e.c                          |   5 +-
 hw/riscv/sifive_u.c                          | 142 ++++++++++++++++-----------
 hw/riscv/spike.c                             |  30 +++++-
 hw/riscv/virt.c                              |   6 +-
 include/hw/riscv/boot.h                      |   6 +-
 include/hw/riscv/sifive_u.h                  |   3 +
 linux-user/riscv/signal.c                    |   3 +-
 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 49472 -> 49520 bytes
 pc-bios/opensbi-riscv32-virt-fw_jump.bin     | Bin 41280 -> 49504 bytes
 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 53760 -> 57936 bytes
 pc-bios/opensbi-riscv64-virt-fw_jump.bin     | Bin 49664 -> 57920 bytes
 roms/opensbi                                 |   2 +-
 target/riscv/cpu.c                           |  10 ++
 target/riscv/cpu.h                           |   1 +
 target/riscv/cpu_helper.c                    |  18 ++--
 16 files changed, 159 insertions(+), 80 deletions(-)


^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-04-30 12:10 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-04-29 20:19 [PULL v2 00/14] RISC-V Patch Queue for 5.1 Alistair Francis
2020-04-29 20:19 ` [PULL v2 01/14] riscv/sifive_u: Fix up file ordering Alistair Francis
2020-04-29 20:19 ` [PULL v2 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC Alistair Francis
2020-04-29 20:19 ` [PULL v2 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine Alistair Francis
2020-04-29 20:19 ` [PULL v2 04/14] riscv: Don't use stage-2 PTE lookup protection flags Alistair Francis
2020-04-29 20:19 ` [PULL v2 05/14] riscv: AND stage-1 and stage-2 " Alistair Francis
2020-04-29 20:19 ` [PULL v2 06/14] riscv: Fix Stage2 SV32 page table walk Alistair Francis
2020-04-29 20:19 ` [PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines Alistair Francis
2020-04-29 20:20 ` [PULL v2 08/14] riscv: sifive_e: Support changing CPU type Alistair Francis
2020-04-29 20:20 ` [PULL v2 09/14] target/riscv: Add a sifive-e34 cpu type Alistair Francis
2020-04-29 20:20 ` [PULL v2 10/14] linux-user/riscv: fix up struct target_ucontext definition Alistair Francis
2020-04-29 20:20 ` [PULL v2 11/14] roms: opensbi: Upgrade from v0.6 to v0.7 Alistair Francis
2020-04-29 20:20 ` [PULL v2 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() Alistair Francis
2020-04-29 20:20 ` [PULL v2 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option Alistair Francis
2020-04-29 20:20 ` [PULL v2 14/14] hw/riscv/spike: Allow more than one CPUs Alistair Francis
2020-04-30 11:52 ` [PULL v2 00/14] RISC-V Patch Queue for 5.1 Peter Maydell

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