From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/12] riscv-to-apply queue
Date: Thu, 7 Nov 2024 20:44:58 +0000 [thread overview]
Message-ID: <CAFEAcA8h530-M8f0GOOJ3=TQPB7Ae0O65P=k2sZZXUx562D4MQ@mail.gmail.com> (raw)
In-Reply-To: <20241107041016.40800-1-alistair.francis@wdc.com>
On Thu, 7 Nov 2024 at 04:11, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit 63dc36944383f70f1c7a20f6104966d8560300fa:
>
> Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging (2024-11-06 17:28:45 +0000)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241107
>
> for you to fetch changes up to 27652f9ca9d831c67dd447346c6ee953669255f0:
>
> tests/functional: Convert the RV32-on-RV64 riscv test (2024-11-07 13:12:58 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.2
>
> * Fix broken SiFive UART on big endian hosts
> * Fix IOMMU Coverity issues
> * Improve the performance of vector unit-stride/whole register ld/st instructions
> * Update kvm exts to Linux v6.11
> * Convert the RV32-on-RV64 riscv test
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2
for any user-visible changes.
-- PMM
next prev parent reply other threads:[~2024-11-07 20:46 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-07 4:10 [PULL 00/12] riscv-to-apply queue Alistair Francis
2024-11-07 4:10 ` [PULL 01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts Alistair Francis
2024-11-07 4:10 ` [PULL 02/12] hw/riscv/riscv-iommu: change 'depth' to int Alistair Francis
2024-11-07 4:10 ` [PULL 03/12] hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check Alistair Francis
2024-11-07 4:10 ` [PULL 04/12] target/riscv: Set vdata.vm field for vector load/store whole register instructions Alistair Francis
2024-11-07 4:10 ` [PULL 05/12] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us Alistair Francis
2024-11-07 4:10 ` [PULL 06/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store Alistair Francis
2024-11-07 4:10 ` [PULL 07/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store Alistair Francis
2024-11-07 4:10 ` [PULL 08/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions Alistair Francis
2024-11-07 4:10 ` [PULL 09/12] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions Alistair Francis
2024-11-07 4:10 ` [PULL 10/12] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Alistair Francis
2024-11-07 4:10 ` [PULL 11/12] target/riscv/kvm: Update kvm exts to Linux v6.11 Alistair Francis
2024-11-07 4:10 ` [PULL 12/12] tests/functional: Convert the RV32-on-RV64 riscv test Alistair Francis
2024-11-07 20:44 ` Peter Maydell [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-09-23 4:06 [PULL 00/12] riscv-to-apply queue Alistair Francis
2022-09-26 19:28 ` Stefan Hajnoczi
2022-09-26 20:59 ` Alistair Francis
2022-09-26 21:04 ` Stefan Hajnoczi
2021-01-17 21:53 Alistair Francis
2021-01-18 12:03 ` Peter Maydell
2020-10-23 15:16 Alistair Francis
2020-10-26 13:16 ` Peter Maydell
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