From: Peter Maydell <peter.maydell@linaro.org>
To: Alireza Sanaee <alireza.sanaee@huawei.com>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, linuxarm@huawei.com,
richard.henderson@linaro.org,
shameerali.kolothum.thodi@huawei.com,
Jonathan.Cameron@huawei.com, alex.bennee@linaro.org,
philmd@linaro.org, jiangkunkun@huawei.com
Subject: Re: [PATCH v5] target/arm/tcg: refine cache descriptions with a wrapper
Date: Fri, 6 Sep 2024 16:33:02 +0100 [thread overview]
Message-ID: <CAFEAcA8ip=+d6JwZJ71P=nUsUa4o2x_7LsWxoqzpnSY7C2G9AQ@mail.gmail.com> (raw)
In-Reply-To: <20240903144550.280-1-alireza.sanaee@huawei.com>
On Tue, 3 Sept 2024 at 15:45, Alireza Sanaee <alireza.sanaee@huawei.com> wrote:
>
> This patch allows for easier manipulation of the cache description
> register, CCSIDR. Which is helpful for testing as well. Currently,
> numbers get hard-coded and might be prone to errors.
>
> Therefore, this patch adds a wrapper for different types of CPUs
> available in tcg to decribe caches. One function `make_ccsidr` supports
> two cases by carrying a parameter as FORMAT that can be LEGACY and
> CCIDX which determines the specification of the register.
>
> For CCSIDR register, 32 bit version follows specification [1].
> Conversely, 64 bit version follows specification [2].
>
> [1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R
> edition, https://developer.arm.com/documentation/ddi0406
> [2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture,
> https://developer.arm.com/documentation/ddi0487/latest/
>
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2024-09-06 15:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-03 14:45 [PATCH v5] target/arm/tcg: refine cache descriptions with a wrapper Alireza Sanaee via
2024-09-03 15:23 ` Philippe Mathieu-Daudé
2024-09-06 15:33 ` Peter Maydell [this message]
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