Re: [PATCH 1/1] hw/arm/sbsa-ref: add PCIe node into DT

[Peter Maydell <peter.maydell@linaro.org>]

On Tue, 27 Jun 2023 at 14:27, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 27 Jun 2023 at 13:52, Leif Lindholm <quic_llindhol@quicinc.com> wrote:
> >
> > On 2023-06-27 13:12, Peter Maydell wrote:
> > > On Mon, 26 Jun 2023 at 08:52, Marcin Juszkiewicz
> > > <marcin.juszkiewicz@linaro.org> wrote:
> > >>
> > >> Add PCI Express information into DeviceTree as part of SBSA-REF
> > >> versioning.
> > >>
> > >> Trusted Firmware will read it and provide to next firmware level.
> > >>
> > >> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> > >> ---
> > >>   hw/arm/sbsa-ref.c | 20 ++++++++++++++++++++
> > >>   1 file changed, 20 insertions(+)
> > >>
> > >> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> > >> index 0639f97dd5..b87d2ee3b2 100644
> > >> --- a/hw/arm/sbsa-ref.c
> > >> +++ b/hw/arm/sbsa-ref.c
> > >> @@ -171,6 +171,25 @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
> > >>       return arm_cpu_mp_affinity(idx, clustersz);
> > >>   }
> > >>
> > >> +static void sbsa_fdt_add_pcie_node(SBSAMachineState *sms)
> > >> +{
> > >> +    char *nodename;
> > >> +
> > >> +    nodename = g_strdup_printf("/pcie");
> > >> +    qemu_fdt_add_subnode(sms->fdt, nodename);
> > >> +    qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_ECAM].base,
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_ECAM].size,
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_PIO].base,
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_PIO].size,
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_MMIO].base,
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_MMIO].size,
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base,
> > >> +                                 2, sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size);
> > >> +
> > >> +    g_free(nodename);
> > >
> > >
> > > Why do we need to do this? The firmware should just
> > > know exactly where the PCIE windows are, the same way
> > > it knows where the flash, the UART, the RTC etc etc
> > > all are in the memory map.
> >
> > That is not automatically true (it was not for at least one SoC I have
> > worked on). In a real system which had these dynamically decided, some
> > coprocessor would program the CMN to route these address ranges to
> > certain offsets within certain components, and that same coprocessor
> > could then provide a mechanism for how TF-A could discover these and
> > provide it to later-stage firmware via SiP SMC calls.
> >
> > Sticking the information in the DT lets us emulate this without actually
> > emulating the CMN and the coprocessor, and prototype (and verify) the
> > same firmware interfaces for developing i.e. edk2 support.
>
> OK. This is the kind of rationale that needs to be described
> in the commit message and comments, though, so it's clear
> why the PCI controller is special in this way.

Just to be clear about the status of this patch, I don't
have a problem with the code changes, but it does definitely
need a much clearer commit message to explain why we're changing
the way we handle the PCI controller. So I'm dropping this from
my to-review list on the assumption there will be a v2.

We could also do with expanding the commentary in the source
file to clarify the design approach we're using w.r.t. what
we do and don't want to put into the "dt" blob, but that would
probably be best in a different patch.

thanks
-- PMM