From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38632) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZc0R-0005kO-EN for qemu-devel@nongnu.org; Fri, 03 Feb 2017 06:26:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZc0Q-0003l8-Fu for qemu-devel@nongnu.org; Fri, 03 Feb 2017 06:26:19 -0500 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]:36273) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cZc0Q-0003kL-9o for qemu-devel@nongnu.org; Fri, 03 Feb 2017 06:26:18 -0500 Received: by mail-wm0-x233.google.com with SMTP id c85so23924812wmi.1 for ; Fri, 03 Feb 2017 03:26:18 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20170201150553.9381-26-alex.bennee@linaro.org> References: <20170201150553.9381-1-alex.bennee@linaro.org> <20170201150553.9381-26-alex.bennee@linaro.org> From: Peter Maydell Date: Fri, 3 Feb 2017 11:25:56 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v9 25/25] tcg: enable MTTCG by default for ARM on x86 hosts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?QWxleCBCZW5uw6ll?= Cc: MTTCG Devel , QEMU Developers , =?UTF-8?B?S09OUkFEIEZyw6lkw6lyaWM=?= , Alvise Rigo , "Emilio G. Cota" , Pranith Kumar , Nikunj A Dadhania , Mark Burton , Paolo Bonzini , Jan Kiszka , Fedorov Sergey , Richard Henderson , Bamvor Zhang Jian , Peter Crosthwaite , "open list:ARM" On 1 February 2017 at 15:05, Alex Benn=C3=A9e wrot= e: > This enables the multi-threaded system emulation by default for ARMv7 > and ARMv8 guests using the x86_64 TCG backend. This is because on the > guest side: > > - The ARM translate.c/translate-64.c have been converted to > - use MTTCG safe atomic primitives > - emit the appropriate barrier ops > - The ARM machine has been updated to > - hold the BQL when modifying shared cross-vCPU state > - defer cpu_reset to async safe work > > All the host backends support the barrier and atomic primitives but > need to provide same-or-better support for normal load/store > operations. > diff --git a/cpus.c b/cpus.c > index e3d9f3fe21..e1b82bcd49 100644 > --- a/cpus.c > +++ b/cpus.c > @@ -176,8 +176,8 @@ bool mttcg_enabled; > > static bool check_tcg_memory_orders_compatible(void) > { > -#if defined(TCG_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) > - return (TCG_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) =3D=3D 0; > +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) > + return (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) =3D=3D 0; This looks like maybe something that should have been squashed into an earlier part of the patchset? > #else > return false; > #endif > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index a3c4d07817..0ef31db3e0 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -30,6 +30,9 @@ > # define TARGET_LONG_BITS 32 > #endif > > +/* ARM processors have a weak memory model */ > +#define TCG_GUEST_DEFAULT_MO (0) Do you need the () ? That said, if Richard is happy with turning this on then I'm happy to do so. Acked-by: Peter Maydell thanks -- PMM