From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkFPQ-0000qY-2x for qemu-devel@nongnu.org; Fri, 31 Oct 2014 12:50:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XkFPH-0007Hf-Md for qemu-devel@nongnu.org; Fri, 31 Oct 2014 12:50:44 -0400 Received: from mail-lb0-f169.google.com ([209.85.217.169]:56948) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkFPH-0007Ha-Cc for qemu-devel@nongnu.org; Fri, 31 Oct 2014 12:50:35 -0400 Received: by mail-lb0-f169.google.com with SMTP id p9so769342lbv.28 for ; Fri, 31 Oct 2014 09:50:34 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1414704538-17103-4-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> <1414704538-17103-4-git-send-email-greg.bellows@linaro.org> From: Peter Maydell Date: Fri, 31 Oct 2014 16:50:13 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v8 03/27] target-arm: add banked register accessors List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: Sergey Fedorov , QEMU Developers , Fabian Aggeler , "Edgar E. Iglesias" On 30 October 2014 21:28, Greg Bellows wrote: > From: Fabian Aggeler > > If EL3 is in AArch32 state certain cp registers are banked (secure and > non-secure instance). When reading or writing to coprocessor registers > the following macros can be used. > > - A32_BANKED macros are used for choosing the banked register based on provided > input security argument. This macro is used to choose the bank during > translation of MRC/MCR instructions that are dependent on something other > than the current secure state. > - A32_BANKED_CURRENT macros are used for choosing the banked register based on > current secure state. This is NOT to be used for choosing the bank used > during translation as it breaks monitor mode. > > If EL3 is operating in AArch64 state coprocessor registers are not > banked anymore. The macros use the non-secure instance (_ns) in this > case, which is architecturally mapped to the AArch64 EL register. > > Signed-off-by: Sergey Fedorov > Signed-off-by: Fabian Aggeler > Signed-off-by: Greg Bellows > Reviewed-by: Peter Maydell > > --- > > v7 -> v8 > - Move use_secure_reg() function to the TBFLAG patch. > > v5 -> v6 > - Converted macro USE_SECURE_REG() into inlince function use_secure_reg() > - Globally replace Aarch# with AArch# > > v4 -> v5 > - Cleaned-up macros to try and alleviate misuse. Made A32_BANKED macros take > secure arg indicator rather than relying on USE_SECURE_REG. Incorporated the > A32_BANKED macros into the A32_BANKED_CURRENT. CURRENT is now the only one > that automatically chooses based on current secure state. > --- > target-arm/cpu.h | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index be5d022..5117d4d 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -817,6 +817,33 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) > return arm_feature(env, ARM_FEATURE_AARCH64); > } > > +/* Macros for accessing a specified CP register bank */ > +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ > + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) > + > +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ > + do { \ > + if (_secure) { \ > + (_env)->cp15._regname##_s = (_val); \ > + } else { \ > + (_env)->cp15._regname##_ns = (_val); \ > + } \ > + } while (0) It's just occurred to me that this probably needs to be doing a deposit32(), because where an AArch32 register is architecturally mapped to an AArch64 register then only the appropriate 32 bits of the AArch64 reg get modified by setting the 32 bit value. > +/* Macros for automatically accessing a specific CP register bank depending on > + * the current secure state of the system. These macros are not intended for > + * supporting instruction translation reads/writes as these are dependent > + * solely on the SCR.NS bit and not the mode. > + */ > +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ > + A32_BANKED_REG_GET((_env), _regname, \ > + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) > + > +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ > + A32_BANKED_REG_SET((_env), _regname, \ > + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ > + (_val)) > + > void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); > unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); -- PMM