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From: Peter Maydell <peter.maydell@linaro.org>
To: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v5 10/10] test: tpm-tis: Add Sysbus TPM-TIS device test
Date: Thu, 12 May 2022 14:08:54 +0100	[thread overview]
Message-ID: <CAFEAcA8pC4RQ3oVVVzG4NA8fBkhzspxD+DyZB+UCn7u1aPSP5A@mail.gmail.com> (raw)
In-Reply-To: <20200305165149.618-11-eric.auger@redhat.com>

On Thu, 5 Mar 2020 at 16:52, Eric Auger <eric.auger@redhat.com> wrote:
>
> The tests themselves are the same as the ISA device ones.
> Only the main() changes as the "tpm-tis-device" device gets
> instantiated. Also the base address of the device is not
> 0xFED40000 anymore but matches the base address of the
> ARM virt platform bus.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>

Hi Eric; the commit adding this test is from back in 2020, but I've
just noticed something a bit odd about it:

> +    args = g_strdup_printf(
> +        "-machine virt,gic-version=max -accel tcg "
> +        "-chardev socket,id=chr,path=%s "
> +        "-tpmdev emulator,id=dev,chardev=chr "
> +        "-device tpm-tis-device,tpmdev=dev",
> +        test.addr->u.q_unix.path);

This 'virt' command line doesn't specify a CPU type, so it
will end up running with a Cortex-A15 (32-bit). Was
that intended? Also, it will get a GICv3, which is a
definitely odd combination with an A15, which was a GICv2 CPU...

I noticed this because I have some recent GICv3 patches which
end up asserting if the GICv3 and a non-GICv3 CPU are used together,
and this test case triggers them. Since the user can also cause
an assert with that kind of command line I'm going to rework them
(either to make the virt board fail cleanly or else to make the
GICv3 code do something plausible even if the real hardware CPU
nominally didn't have a GICv3). But maybe we should make this
test case not use a non-standard combination anyway? (The meson
conversion seems to have resulted in this test being run under
qemu-system-arm as well, incidentally, so I guess we would want
it to specify either 'a 64 bit CPU and GICv3' or 'a 32 bit
CPU and GICv2' accordingly. Or limit the test to aarch64...)

thanks
-- PMM


  reply	other threads:[~2022-05-12 13:11 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-05 16:51 [PATCH v5 00/10] vTPM for aarch64 Eric Auger
2020-03-05 16:51 ` [PATCH v5 01/10] tpm: rename TPM_TIS into TPM_TIS_ISA Eric Auger
2020-03-05 16:51 ` [PATCH v5 02/10] tpm: Use TPMState as a common struct Eric Auger
2020-03-05 16:51 ` [PATCH v5 03/10] tpm: Separate tpm_tis common functions from isa code Eric Auger
2020-03-05 16:51 ` [PATCH v5 04/10] tpm: Separate TPM_TIS and TPM_TIS_ISA configs Eric Auger
2020-03-05 16:51 ` [PATCH v5 05/10] tpm: Add the SysBus TPM TIS device Eric Auger
2020-03-05 16:51 ` [PATCH v5 06/10] hw/arm/virt: vTPM support Eric Auger
2020-03-05 16:51 ` [PATCH v5 07/10] docs/specs/tpm: Document TPM_TIS sysbus device for ARM Eric Auger
2020-03-05 16:51 ` [PATCH v5 08/10] test: tpm: pass optional machine options to swtpm test functions Eric Auger
2020-03-05 16:51 ` [PATCH v5 09/10] test: tpm-tis: Get prepared to share tests between ISA and sysbus devices Eric Auger
2020-03-05 16:51 ` [PATCH v5 10/10] test: tpm-tis: Add Sysbus TPM-TIS device test Eric Auger
2022-05-12 13:08   ` Peter Maydell [this message]
2022-05-12 15:59     ` Eric Auger
2022-05-12 16:05       ` Peter Maydell
2022-05-13  7:51         ` Igor Mammedov
2020-03-05 18:05 ` [PATCH v5 00/10] vTPM for aarch64 Stefan Berger

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