From: Peter Maydell <peter.maydell@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com, philmd@linaro.org,
alex.bennee@linaro.org
Subject: Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
Date: Wed, 24 Jul 2024 19:22:24 +0100 [thread overview]
Message-ID: <CAFEAcA8pdw1zUxMXD1g08TedNo7MizUXOSJF6eciuCU=c2zx7Q@mail.gmail.com> (raw)
In-Reply-To: <20240719231149.1364-8-zhiwei_liu@linux.alibaba.com>
On Sat, 20 Jul 2024 at 00:18, LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is that
> we want to follow the RISC-V custom where addw instruction doesn't
> exist in RV32 CPU.
You might want to consider whether you'd rather have this be
"-cpu max,64=off" (replace "64" with whatever feature name the
architecture uses for 64-bit support). That's the way I would plan
to handle it for Arm (with "-cpu max,aarch64=off"; that works for
KVM right now and if we ever wanted to handle it for TCG would be how
I'd want the command line syntax to go).
-- PMM
next prev parent reply other threads:[~2024-07-24 18:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-19 23:11 [PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 6/8] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-19 23:11 ` [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for " LIU Zhiwei
2024-07-20 9:24 ` Daniel Henrique Barboza
2024-07-24 15:01 ` Andrew Jones
2024-07-25 1:53 ` LIU Zhiwei
2024-07-24 18:22 ` Peter Maydell [this message]
2024-07-19 23:11 ` [PATCH v6 8/8] tests/avocado: Boot Linux for RV32 cpu on " LIU Zhiwei
2024-07-20 9:24 ` Daniel Henrique Barboza
2024-07-25 10:27 ` Alex Bennée
2024-07-24 2:44 ` [PATCH v6 0/8] target/riscv: Expose RV32 cpu to " Alistair Francis
2024-07-25 7:01 ` Philippe Mathieu-Daudé
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