From: Peter Maydell <peter.maydell@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: Xiangyu Hu <libhu.so@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] FMULX should flushes operators to zero when FZ is set.
Date: Thu, 29 Jan 2015 19:22:34 +0000 [thread overview]
Message-ID: <CAFEAcA8pzvqaO3wHG4udQXj8vpaSJD2D33-8==s_GqfDbx2A-g@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA84cqR2WEG=15SAF9PfbMn_QO_6QQCbrX1j0Q2qoZ4dhA@mail.gmail.com>
On 28 January 2015 at 15:57, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 January 2015 at 15:54, Alex Bennée <alex.bennee@linaro.org> wrote:
>> Do we have test cases that trip up here? It would be nice to include
>> them in our testing as the random nature of RISU has obviously failed to
>> trip up on this instruction.
>
> Risu would probably catch this if we generated and ran test cases
> which set the FPSCR bits to something other than the default.
This bug is indeed caught by the following risugen:
./risugen --numinsns 10000 --pattern "FMULX A64_V" --fpscr 0x01000000
aarch64.risu FMULX_S3SAME_V_squash.out
(that fpscr value being "set DZ, nothing else".)
Alex, I don't suppose your automation of these tests makes
it easy to do a complete extra run (or better, just of the
Neon and FP insn tests) with different FPSCR flags?
-- PMM
next prev parent reply other threads:[~2015-01-29 19:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-28 14:51 [Qemu-devel] [PATCH] FMULX should flushes operators to zero when FZ is set Xiangyu Hu
2015-01-28 14:54 ` Peter Maydell
2015-01-28 15:42 ` Xiangyu Hu
2015-01-28 15:54 ` Alex Bennée
2015-01-28 15:57 ` Peter Maydell
2015-01-28 16:11 ` Xiangyu Hu
2015-01-28 16:12 ` Claudio Fontana
2015-01-28 16:25 ` Peter Maydell
2015-01-29 19:22 ` Peter Maydell [this message]
2015-02-03 13:44 ` Alex Bennée
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