From: Peter Maydell <peter.maydell@linaro.org>
To: "Clément Chigot" <chigot@adacore.com>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
edgar.iglesias@gmail.com, alistair@alistair23.me
Subject: Re: [PATCH 4/4] hw/arm/xlnx-zynqmp: adapt cluster-id based on the boot cpu
Date: Mon, 19 May 2025 16:37:51 +0100 [thread overview]
Message-ID: <CAFEAcA8qA-ZyWihgSkw3Ubnz-WyXMB3m_MT9facnktqbXAM7MA@mail.gmail.com> (raw)
In-Reply-To: <20250513141448.297946-5-chigot@adacore.com>
On Tue, 13 May 2025 at 15:15, Clément Chigot <chigot@adacore.com> wrote:
>
> When gdb is being connected to QEmu, it will be attached to the first
(QEMU is all-caps, by the way)
> CPU cluster. However, the ZynqMP board has two clusters, those being of
> two different architectures.
> Therefore, when gdb is connecting to the ZynqMP, it receives the target
> descriptor of the first CPU cluster. Up to now, it was always the APU
> cluster, which is AARCH64.
>
> When booting on a RPU, gdb will still connect to the APU. If gdb is
> supporting only ARM32, it will receive the APU target descriptor,
> resulting in:
> | (gdb) target remote :1234
> | warning: while parsing target description (at line 1): Target
> | description specified unknown architecture "aarch64"
>
> Adjust the cluster-id based on the boot cpu will resolve the above
> issue; allowing a pure ARM32 toolchain to debug programs running on
> RPUs.
I'm not really enthusiastic about renumbering the clusters
like this. I think you should be able to get gdb to connect
to the second cluster via the multiple-inferior support:
https://www.qemu.org/docs/master/system/gdb.html#debugging-multicore-machines
thanks
-- PMM
next prev parent reply other threads:[~2025-05-19 15:38 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 14:14 [PATCH 0/4] xlnx-zynqmp: add support to boot on RPUs Clément Chigot
2025-05-13 14:14 ` [PATCH 1/4] hw/arm: make cpu targeted by arm_load_kernel the primary CPU Clément Chigot
2025-05-19 14:57 ` Peter Maydell
2025-05-13 14:14 ` [PATCH 2/4] hw/intc/arm_gic: introduce a first-cpu-index property Clément Chigot
2025-05-13 15:39 ` Philippe Mathieu-Daudé
2025-05-14 12:41 ` Clément Chigot
2025-05-16 11:37 ` Philippe Mathieu-Daudé
2025-05-19 16:26 ` Peter Maydell
2025-05-20 8:58 ` Edgar E. Iglesias
2025-05-13 14:14 ` [PATCH 3/4] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5 Clément Chigot
2025-05-13 14:14 ` [PATCH 4/4] hw/arm/xlnx-zynqmp: adapt cluster-id based on the boot cpu Clément Chigot
2025-05-19 15:37 ` Peter Maydell [this message]
2025-05-20 12:41 ` Clément Chigot
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