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From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 27 Apr 2018 13:26:01 +0100
Message-ID: <CAFEAcA8sadsm3SkoZLVk0qWWxfnGAHFbofpxV08QxVpyjZTZkA@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v8 04/23] RISC-V Disassembler
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To: Michael Clark <mjc@sifive.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org>

On 2 March 2018 at 13:51, Michael Clark <mjc@sifive.com> wrote:
> The RISC-V disassembler has no dependencies outside of the 'disas'
> directory so it can be applied independently. The majority of the
> disassembler is machine-generated from instruction set metadata:
>
> - https://github.com/michaeljclark/riscv-meta

> +        case 5:
> +            if (isa == rv128) {
> +                op = rv_op_c_sqsp;
> +            } else {
> +                op = rv_op_c_fsdsp; break;
> +            }
> +        case 6: op = rv_op_c_swsp; break;

Coverity (CID1390575) points out that for the
case 5 / isa == rv128 codepath, we set op, and
then fall through into case 6 which overwrites it.

Is there a missing "break" statement here? (If the
fallthrough is deliberate it should be marked with a
/* fallthrough */ comment.)

thanks
-- PMM