From: Peter Maydell <peter.maydell@linaro.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3
Date: Mon, 1 Jul 2019 17:54:40 +0100 [thread overview]
Message-ID: <CAFEAcA8sscJQ2GCwL1gM+EcRtfHQb1v0BwORt6ncH54x51TCVg@mail.gmail.com> (raw)
In-Reply-To: <20190627152011.18686-34-palmer@sifive.com>
On Thu, 27 Jun 2019 at 16:24, Palmer Dabbelt <palmer@sifive.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
> ---
> .gitmodules | 3 ++
> Makefile | 5 +-
> pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 0 -> 28848 bytes
> pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 0 -> 28904 bytes
> pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 0 -> 28904 bytes
> roms/Makefile | 48 ++++++++++++++-----
> roms/opensbi | 1 +
> 7 files changed, 44 insertions(+), 13 deletions(-)
> create mode 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin
> create mode 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
> create mode 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin
> create mode 160000 roms/opensbi
>
> diff --git a/.gitmodules b/.gitmodules
> index 2857eec76377..7a10e72e09cd 100644
> --- a/.gitmodules
> +++ b/.gitmodules
> @@ -55,3 +55,6 @@
> [submodule "slirp"]
> path = slirp
> url = https://git.qemu.org/git/libslirp.git
> +[submodule "roms/opensbi"]
> + path = roms/opensbi
> + url = https://github.com/riscv/opensbi.git
It would be nice to state the license for new blobs we're
adding to the source tree... In particular, I find the
readme at https://github.com/riscv/opensbi a bit confusing
because it says it's 2-BSD but also that some parts are Apache-2.0;
the latter is *not* GPL-2.0 compatible. That makes it not completely
obvious to me that we can ship this with QEMU.
Also, new git modules in .gitmodules should be qemu.org
URLs, not random external ones. (ie, we should set up
mirroring of any new external repo we start shipping
code and binaries for). We can set this up and fix up the
gitmodules file after the fact, but the ideal is to do
it in advance rather than afterwards.
thanks
-- PMM
next prev parent reply other threads:[~2019-07-01 21:13 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 15:19 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 02/34] sifive_prci: Read and write PRCI registers Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 03/34] target/riscv: Fix PMP range boundary address bug Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 08/34] RISC-V: Check PMP during Page Table Walks Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size Palmer Dabbelt
2019-06-27 17:44 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-06-27 18:23 ` Richard Henderson
2019-07-08 12:46 ` Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 13/34] target/riscv: Restructure deprecatd CPUs Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0 Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 15/34] target/riscv: Add the mcountinhibit CSR Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 18/34] target/riscv: Require either I or E base extension Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 19/34] target/riscv: Remove user version information Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 21/34] RISC-V: Add support for the Zifencei extension Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 22/34] RISC-V: Add support for the Zicsr extension Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 24/34] RISC-V: Update syscall list for 32-bit support Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 25/34] riscv: virt: Add cpu-topology DT node Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 30/34] hw/riscv: Split out the boot functions Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 31/34] hw/riscv: Add support for loading a firmware Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 32/34] hw/riscv: Extend the kernel loading support Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3 Palmer Dabbelt
2019-06-28 9:46 ` Jonathan Cameron
2019-06-28 16:12 ` Alistair Francis
2019-06-28 17:10 ` Palmer Dabbelt
2019-07-01 12:40 ` Jonathan Cameron
2019-07-01 13:23 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-07-01 16:39 ` Alistair Francis
2019-07-01 16:54 ` Peter Maydell [this message]
2019-07-01 17:50 ` [Qemu-devel] " Alistair Francis
2019-07-01 18:01 ` Peter Maydell
2019-07-01 18:09 ` Alistair Francis
2019-07-01 18:13 ` Peter Maydell
2019-07-01 18:19 ` Alistair Francis
2019-07-02 7:02 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-07-02 4:12 ` [Qemu-devel] " Markus Armbruster
2019-07-02 10:32 ` Paolo Bonzini
2019-07-02 16:07 ` Alistair Francis
2019-07-04 16:00 ` Stefan Hajnoczi
2019-07-04 19:35 ` Alistair Francis
2019-06-27 15:20 ` [Qemu-devel] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2019-06-28 17:31 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 Palmer Dabbelt
2019-06-28 17:32 ` [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3 Palmer Dabbelt
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