From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyS1g-0000nl-Us for qemu-devel@nongnu.org; Fri, 29 May 2015 17:41:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyS1d-0003MJ-Ij for qemu-devel@nongnu.org; Fri, 29 May 2015 17:41:12 -0400 Received: from mail-ig0-f180.google.com ([209.85.213.180]:33341) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyS1d-0003MF-E5 for qemu-devel@nongnu.org; Fri, 29 May 2015 17:41:09 -0400 Received: by igbpi8 with SMTP id pi8so24876926igb.0 for ; Fri, 29 May 2015 14:41:08 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <2816EEF2-0256-4B49-8811-74EFB3016CD4@livius.net> <20150529111118.7f116572@nial.brq.redhat.com> <7A249492-B5F2-46D5-92A2-12BB30202C5F@livius.net> From: Peter Maydell Date: Fri, 29 May 2015 22:40:48 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [RFC] extensions to the -m memory option List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Liviu Ionescu Cc: Igor Mammedov , QEMU Developers On 29 May 2015 at 21:26, Liviu Ionescu wrote: >> On 29 May 2015, at 22:32, Peter Maydell wrote: >> RAM and flash size is not a property of the CPU -- the M3 itself >> has no builtin memory. RAM and flash are external to the CPU and >> are part of the SoC, so the CPU would be the wrong place to specify >> their sizes. > > ok, probably according to the dictionary you are right. > > however, in the microcontroller world, it is usual to abuse the terms > and use CPU for MCU. > > also, from a pure linguistic point of view, although microcontrollers > (having plenty of memory and countless peripherals) can be considered > "SoC", my understanding is that usually SoC is more appropriate for > 'systems' running an operating system (most of the time linux), than > to MCUs running a simple scheduler. The important distinction is not linguistic but in how we model things. There is a set of layers: 1) the CPU is the set of things in a Cortex-M3 (in this case), as defined by the technical reference manual for the processor; that has the registers and the MPU and so on in it 2) what I call the "SoC" and which in the microcontroller world is called the MCU is the bit of silicon which contains: * a CPU * various devices like a UART and others * probably flash, maybe RAM 3) a "board", which has the SoC/MCU chip on it, and likely some other chips, but perhaps none; if the RAM isn't built into the SoC then it's on the board QEMU models these in layers because the hardware is in layers. The RAM and flash are not in the Cortex-M3 in our model, because they're not in the M3 in real life either. "SoC" just means "system on chip", ie "one chip, with a CPU and enough devices on it to be a more-or-less complete system". (You don't need an SoC for a system in theory, you could build one with a separate CPU and devices all on their own chips, but in practice ARM CPUs tend to come in SoCs.) Whether you call it an SoC or an MCU, the key point is that there's a level of abstraction, a container, between the CPU itself and the board. That's where the RAM and flash usually live and that's where the properties to control their size probably belong. -- PMM