* [PULL 00/36] target-arm queue
@ 2020-03-12 16:44 Peter Maydell
2020-03-12 20:32 ` Peter Maydell
0 siblings, 1 reply; 49+ messages in thread
From: Peter Maydell @ 2020-03-12 16:44 UTC (permalink / raw)
To: qemu-devel
arm queue; dunno if this will be the last before softfreeze
or not, but anyway probably the last large one. New orangepi-pc
board model is the big item here.
thanks
-- PMM
The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix various bugs that might result in an assert() due to
incorrect hflags for M-profile CPUs
* Fix Aspeed SMC Controller user-mode select handling
* Report correct (with-tag) address in fault address register
when TBI is enabled
* cubieboard: make sure SOC object isn't leaked
* fsl-imx25: Wire up eSDHC controllers
* fsl-imx25: Wire up USB controllers
* New board model: orangepi-pc (OrangePi PC)
* ARM/KVM: if user doesn't select GIC version and the
host kernel can only provide GICv3, use that, rather
than defaulting to "fail because GICv2 isn't possible"
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
----------------------------------------------------------------
Beata Michalska (1):
target/arm: kvm: Inject events at the last stage of sync
Cédric Le Goater (2):
aspeed/smc: Add some tracing
aspeed/smc: Fix User mode select/unselect scheme
Eric Auger (6):
hw/arm/virt: Document 'max' value in gic-version property description
hw/arm/virt: Introduce VirtGICType enum type
hw/arm/virt: Introduce finalize_gic_version()
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
hw/arm/virt: kvm: Restructure finalize_gic_version()
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
Guenter Roeck (2):
hw/arm/fsl-imx25: Wire up eSDHC controllers
hw/arm/fsl-imx25: Wire up USB controllers
Igor Mammedov (1):
hw/arm/cubieboard: make sure SOC object isn't leaked
Niek Linnenbank (13):
hw/arm: add Allwinner H3 System-on-Chip
hw/arm: add Xunlong Orange Pi PC machine
hw/arm/allwinner-h3: add Clock Control Unit
hw/arm/allwinner-h3: add USB host controller
hw/arm/allwinner-h3: add System Control module
hw/arm/allwinner: add CPU Configuration module
hw/arm/allwinner: add Security Identifier device
hw/arm/allwinner: add SD/MMC host controller
hw/arm/allwinner-h3: add EMAC ethernet device
hw/arm/allwinner-h3: add Boot ROM support
hw/arm/allwinner-h3: add SDRAM controller device
hw/arm/allwinner: add RTC device support
docs: add Orange Pi PC document
Peter Maydell (4):
hw/intc/armv7m_nvic: Rebuild hflags on reset
target/arm: Update hflags in trans_CPS_v7m()
target/arm: Recalculate hflags correctly after writes to CONTROL
target/arm: Fix some comment typos
Philippe Mathieu-Daudé (5):
tests/boot_linux_console: Add a quick test for the OrangePi PC board
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
Richard Henderson (2):
target/arm: Check addresses for disabled regimes
target/arm: Disable clean_data_tbi for system mode
Makefile.objs | 1 +
hw/arm/Makefile.objs | 1 +
hw/misc/Makefile.objs | 5 +
hw/net/Makefile.objs | 1 +
hw/rtc/Makefile.objs | 1 +
hw/sd/Makefile.objs | 1 +
hw/usb/hcd-ehci.h | 1 +
include/hw/arm/allwinner-a10.h | 4 +
include/hw/arm/allwinner-h3.h | 161 ++++++
include/hw/arm/fsl-imx25.h | 18 +
include/hw/arm/virt.h | 12 +-
include/hw/misc/allwinner-cpucfg.h | 52 ++
include/hw/misc/allwinner-h3-ccu.h | 66 +++
include/hw/misc/allwinner-h3-dramc.h | 106 ++++
include/hw/misc/allwinner-h3-sysctrl.h | 67 +++
include/hw/misc/allwinner-sid.h | 60 +++
include/hw/net/allwinner-sun8i-emac.h | 99 ++++
include/hw/rtc/allwinner-rtc.h | 134 +++++
include/hw/sd/allwinner-sdhost.h | 135 +++++
target/arm/helper.h | 1 +
target/arm/kvm_arm.h | 3 +
hw/arm/allwinner-a10.c | 19 +
hw/arm/allwinner-h3.c | 465 ++++++++++++++++++
hw/arm/cubieboard.c | 18 +
hw/arm/fsl-imx25.c | 56 +++
hw/arm/imx25_pdk.c | 16 +
hw/arm/orangepi.c | 130 +++++
hw/arm/virt.c | 145 ++++--
hw/intc/armv7m_nvic.c | 6 +
hw/misc/allwinner-cpucfg.c | 282 +++++++++++
hw/misc/allwinner-h3-ccu.c | 242 +++++++++
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++
hw/misc/allwinner-h3-sysctrl.c | 140 ++++++
hw/misc/allwinner-sid.c | 168 +++++++
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++
hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++
hw/ssi/aspeed_smc.c | 56 ++-
hw/usb/hcd-ehci-sysbus.c | 17 +
target/arm/helper.c | 49 +-
target/arm/kvm.c | 14 +-
target/arm/kvm32.c | 15 +-
target/arm/kvm64.c | 15 +-
target/arm/translate-a64.c | 11 +
target/arm/translate.c | 14 +-
MAINTAINERS | 9 +
default-configs/arm-softmmu.mak | 1 +
docs/system/arm/orangepi.rst | 253 ++++++++++
docs/system/target-arm.rst | 2 +
hw/arm/Kconfig | 12 +
hw/misc/trace-events | 19 +
hw/net/Kconfig | 3 +
hw/net/trace-events | 10 +
hw/rtc/trace-events | 4 +
hw/sd/trace-events | 7 +
hw/ssi/trace-events | 10 +
tests/acceptance/boot_linux_console.py | 230 +++++++++
57 files changed, 5787 insertions(+), 74 deletions(-)
create mode 100644 include/hw/arm/allwinner-h3.h
create mode 100644 include/hw/misc/allwinner-cpucfg.h
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
create mode 100644 include/hw/misc/allwinner-sid.h
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
create mode 100644 include/hw/rtc/allwinner-rtc.h
create mode 100644 include/hw/sd/allwinner-sdhost.h
create mode 100644 hw/arm/allwinner-h3.c
create mode 100644 hw/arm/orangepi.c
create mode 100644 hw/misc/allwinner-cpucfg.c
create mode 100644 hw/misc/allwinner-h3-ccu.c
create mode 100644 hw/misc/allwinner-h3-dramc.c
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
create mode 100644 hw/misc/allwinner-sid.c
create mode 100644 hw/net/allwinner-sun8i-emac.c
create mode 100644 hw/rtc/allwinner-rtc.c
create mode 100644 hw/sd/allwinner-sdhost.c
create mode 100644 docs/system/arm/orangepi.rst
create mode 100644 hw/ssi/trace-events
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PULL 00/36] target-arm queue
2020-03-12 16:44 Peter Maydell
@ 2020-03-12 20:32 ` Peter Maydell
0 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2020-03-12 20:32 UTC (permalink / raw)
To: QEMU Developers
On Thu, 12 Mar 2020 at 16:45, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> arm queue; dunno if this will be the last before softfreeze
> or not, but anyway probably the last large one. New orangepi-pc
> board model is the big item here.
>
> thanks
> -- PMM
>
> The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
>
> Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
>
> for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
>
> target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix various bugs that might result in an assert() due to
> incorrect hflags for M-profile CPUs
> * Fix Aspeed SMC Controller user-mode select handling
> * Report correct (with-tag) address in fault address register
> when TBI is enabled
> * cubieboard: make sure SOC object isn't leaked
> * fsl-imx25: Wire up eSDHC controllers
> * fsl-imx25: Wire up USB controllers
> * New board model: orangepi-pc (OrangePi PC)
> * ARM/KVM: if user doesn't select GIC version and the
> host kernel can only provide GICv3, use that, rather
> than defaulting to "fail because GICv2 isn't possible"
> * kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PULL 00/36] target-arm queue
@ 2020-09-14 14:06 Peter Maydell
0 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2020-09-14 14:06 UTC (permalink / raw)
To: qemu-devel
Nuvoton new board models, and some more minor stuff. I also put
in the deprecation patches for unicore32 and lm32.
thanks
-- PMM
The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914
for you to fetch changes up to dd44ae00fc5342ed99acb68ec3508f76a71d523a:
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller (2020-09-14 14:27:08 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/misc/a9scu: Do not allow invalid CPU count
* hw/misc/a9scu: Minor cleanups
* hw/timer/armv7m_systick: assert that board code set system_clock_scale
* decodetree: Improve identifier matching
* target/arm: Clean up neon fp insn size field decode
* target/arm: Remove KVM support for 32-bit Arm hosts
* hw/arm/mps2: New board models mps2-an386, mps2-an500
* Deprecate Unicore32 port
* Deprecate lm32 port
* target/arm: Count PMU events when MDCR.SPME is set
* hw/arm: versal-virt: Correct the tx/rx GEM clocks
* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
* xlnx-zynqmp: implement ZynqMP CAN controllers
----------------------------------------------------------------
Aaron Lindsay (1):
target/arm: Count PMU events when MDCR.SPME is set
Edgar E. Iglesias (1):
hw/arm: versal-virt: Correct the tx/rx GEM clocks
Havard Skinnemoen (14):
hw/misc: Add NPCM7xx System Global Control Registers device model
hw/misc: Add NPCM7xx Clock Controller device model
hw/timer: Add NPCM7xx Timer device model
hw/arm: Add NPCM730 and NPCM750 SoC models
hw/arm: Add two NPCM7xx-based machines
roms: Add virtual Boot ROM for NPCM7xx SoCs
hw/arm: Load -bios image as a boot ROM for npcm7xx
hw/nvram: NPCM7xx OTP device model
hw/mem: Stubbed out NPCM7xx Memory Controller model
hw/ssi: NPCM7xx Flash Interface Unit device model
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
docs/system: Add Nuvoton machine documentation
tests/acceptance: console boot tests for quanta-gsj
Peter Maydell (11):
hw/timer/armv7m_systick: assert that board code set system_clock_scale
target/arm: Convert Neon 3-same-fp size field to MO_* in decode
target/arm: Convert Neon VCVT fp size field to MO_* in decode
target/arm: Convert VCMLA, VCADD size field to MO_* in decode
target/arm: Remove KVM support for 32-bit Arm hosts
target/arm: Remove no-longer-reachable 32-bit KVM code
hw/arm/mps2: New board model mps2-an386
hw/arm/mps2: New board model mps2-an500
docs/system/arm/mps2.rst: Make board list consistent
Deprecate Unicore32 port
Deprecate lm32 port
Philippe Mathieu-Daudé (4):
hw/misc/a9scu: Do not allow invalid CPU count
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
Richard Henderson (1):
decodetree: Improve identifier matching
Vikram Garhwal (4):
hw/net/can: Introduce Xilinx ZynqMP CAN controller
xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
docs/system/arm/mps2.rst | 20 +-
docs/system/arm/nuvoton.rst | 92 +++
docs/system/deprecated.rst | 32 +-
docs/system/target-arm.rst | 1 +
configure | 2 +-
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/npcm7xx.h | 112 +++
include/hw/arm/xlnx-zynqmp.h | 8 +
include/hw/mem/npcm7xx_mc.h | 36 +
include/hw/misc/npcm7xx_clk.h | 48 ++
include/hw/misc/npcm7xx_gcr.h | 43 ++
include/hw/net/xlnx-zynqmp-can.h | 78 +++
include/hw/nvram/npcm7xx_otp.h | 79 +++
include/hw/ssi/npcm7xx_fiu.h | 73 ++
include/hw/timer/npcm7xx_timer.h | 78 +++
target/arm/kvm-consts.h | 7 -
target/arm/kvm_arm.h | 6 -
target/arm/neon-dp.decode | 18 +-
target/arm/neon-shared.decode | 18 +-
tests/decode/succ_ident1.decode | 7 +
hw/arm/mps2.c | 97 ++-
hw/arm/npcm7xx.c | 532 +++++++++++++++
hw/arm/npcm7xx_boards.c | 197 ++++++
hw/arm/xlnx-versal-virt.c | 2 +-
hw/arm/xlnx-zcu102.c | 20 +
hw/arm/xlnx-zynqmp.c | 34 +
hw/mem/npcm7xx_mc.c | 84 +++
hw/misc/a9scu.c | 59 +-
hw/misc/npcm7xx_clk.c | 266 ++++++++
hw/misc/npcm7xx_gcr.c | 269 ++++++++
hw/net/can/xlnx-zynqmp-can.c | 1165 ++++++++++++++++++++++++++++++++
hw/nvram/npcm7xx_otp.c | 440 ++++++++++++
hw/ssi/npcm7xx_fiu.c | 572 ++++++++++++++++
hw/timer/armv7m_systick.c | 8 +
hw/timer/npcm7xx_timer.c | 543 +++++++++++++++
target/arm/cpu.c | 101 ++-
target/arm/helper.c | 2 +-
target/arm/kvm.c | 7 -
target/arm/kvm32.c | 595 ----------------
tests/qtest/xlnx-can-test.c | 359 ++++++++++
.gitmodules | 3 +
MAINTAINERS | 18 +
hw/arm/Kconfig | 9 +
hw/arm/meson.build | 1 +
hw/mem/meson.build | 1 +
hw/misc/meson.build | 4 +
hw/misc/trace-events | 8 +
hw/net/can/meson.build | 1 +
hw/nvram/meson.build | 1 +
hw/ssi/meson.build | 1 +
hw/ssi/trace-events | 11 +
hw/timer/meson.build | 1 +
hw/timer/trace-events | 5 +
pc-bios/README | 6 +
pc-bios/meson.build | 1 +
pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
roms/Makefile | 7 +
roms/vbootrom | 1 +
scripts/decodetree.py | 46 +-
target/arm/meson.build | 5 +-
target/arm/translate-neon.c.inc | 42 +-
tests/acceptance/boot_linux_console.py | 83 +++
tests/qtest/meson.build | 1 +
63 files changed, 5584 insertions(+), 783 deletions(-)
create mode 100644 docs/system/arm/nuvoton.rst
create mode 100644 include/hw/arm/npcm7xx.h
create mode 100644 include/hw/mem/npcm7xx_mc.h
create mode 100644 include/hw/misc/npcm7xx_clk.h
create mode 100644 include/hw/misc/npcm7xx_gcr.h
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
create mode 100644 include/hw/nvram/npcm7xx_otp.h
create mode 100644 include/hw/ssi/npcm7xx_fiu.h
create mode 100644 include/hw/timer/npcm7xx_timer.h
create mode 100644 tests/decode/succ_ident1.decode
create mode 100644 hw/arm/npcm7xx.c
create mode 100644 hw/arm/npcm7xx_boards.c
create mode 100644 hw/mem/npcm7xx_mc.c
create mode 100644 hw/misc/npcm7xx_clk.c
create mode 100644 hw/misc/npcm7xx_gcr.c
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
create mode 100644 hw/nvram/npcm7xx_otp.c
create mode 100644 hw/ssi/npcm7xx_fiu.c
create mode 100644 hw/timer/npcm7xx_timer.c
delete mode 100644 target/arm/kvm32.c
create mode 100644 tests/qtest/xlnx-can-test.c
create mode 100644 pc-bios/npcm7xx_bootrom.bin
create mode 160000 roms/vbootrom
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PULL 00/36] target-arm queue
@ 2020-12-10 11:47 Peter Maydell
2020-12-10 12:51 ` Peter Maydell
0 siblings, 1 reply; 49+ messages in thread
From: Peter Maydell @ 2020-12-10 11:47 UTC (permalink / raw)
To: qemu-devel
First pullreq for 6.0: mostly my v8.1M work, plus some other
bits and pieces. (I still have a lot of stuff in my to-review
folder, which I may or may not get to before the Christmas break...)
thanks
-- PMM
The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210
for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/arm/smmuv3: Fix up L1STD_SPAN decoding
* xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
* sbsa-ref: allow to use Cortex-A53/57/72 cpus
* Various minor code cleanups
* hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
* Implement more pieces of ARMv8.1M support
----------------------------------------------------------------
Alex Chen (4):
i.MX25: Fix bad printf format specifiers
i.MX31: Fix bad printf format specifiers
i.MX6: Fix bad printf format specifiers
i.MX6ul: Fix bad printf format specifiers
Havard Skinnemoen (1):
tests/qtest/npcm7xx_rng-test: dump random data on failure
Kunkun Jiang (1):
hw/arm/smmuv3: Fix up L1STD_SPAN decoding
Marcin Juszkiewicz (1):
sbsa-ref: allow to use Cortex-A53/57/72 cpus
Peter Maydell (25):
hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
target/arm: Implement v8.1M PXN extension
target/arm: Don't clobber ID_PFR1.Security on M-profile cores
target/arm: Implement VSCCLRM insn
target/arm: Implement CLRM instruction
target/arm: Enforce M-profile VMRS/VMSR register restrictions
target/arm: Refactor M-profile VMSR/VMRS handling
target/arm: Move general-use constant expanders up in translate.c
target/arm: Implement VLDR/VSTR system register
target/arm: Implement M-profile FPSCR_nzcvqc
target/arm: Use new FPCR_NZCV_MASK constant
target/arm: Factor out preserve-fp-state from full_vfp_access_check()
target/arm: Implement FPCXT_S fp system register
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
target/arm: Implement v8.1M REVIDR register
target/arm: Implement new v8.1M NOCP check for exception return
target/arm: Implement new v8.1M VLLDM and VLSTM encodings
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
target/arm: Implement CCR_S.TRD behaviour for SG insns
hw/intc/armv7m_nvic: Fix "return from inactive handler" check
target/arm: Implement M-profile "minimal RAS implementation"
hw/intc/armv7m_nvic: Implement read/write for RAS register block
hw/arm/armv7m: Correct typo in QOM object name
Vikram Garhwal (4):
hw/net/can: Introduce Xilinx ZynqMP CAN controller
xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
meson.build | 1 +
hw/arm/smmuv3-internal.h | 2 +-
hw/net/can/trace.h | 1 +
include/hw/arm/xlnx-zynqmp.h | 8 +
include/hw/intc/armv7m_nvic.h | 2 +
include/hw/net/xlnx-zynqmp-can.h | 78 +++
target/arm/cpu.h | 46 ++
target/arm/m-nocp.decode | 10 +-
target/arm/t32.decode | 10 +-
target/arm/vfp.decode | 14 +
hw/arm/armv7m.c | 4 +-
hw/arm/sbsa-ref.c | 23 +-
hw/arm/xlnx-zcu102.c | 20 +
hw/arm/xlnx-zynqmp.c | 34 ++
hw/intc/armv7m_nvic.c | 246 ++++++--
hw/misc/imx25_ccm.c | 12 +-
hw/misc/imx31_ccm.c | 14 +-
hw/misc/imx6_ccm.c | 20 +-
hw/misc/imx6_src.c | 2 +-
hw/misc/imx6ul_ccm.c | 4 +-
hw/misc/imx_ccm.c | 4 +-
hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++++++++++
target/arm/cpu.c | 5 +-
target/arm/helper.c | 7 +-
target/arm/m_helper.c | 130 ++++-
target/arm/translate.c | 105 +++-
tests/qtest/npcm7xx_rng-test.c | 12 +
tests/qtest/xlnx-can-test.c | 360 ++++++++++++
MAINTAINERS | 8 +
hw/Kconfig | 1 +
hw/net/can/meson.build | 1 +
hw/net/can/trace-events | 9 +
target/arm/translate-vfp.c.inc | 511 ++++++++++++++++-
tests/qtest/meson.build | 1 +
34 files changed, 2713 insertions(+), 153 deletions(-)
create mode 100644 hw/net/can/trace.h
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
create mode 100644 tests/qtest/xlnx-can-test.c
create mode 100644 hw/net/can/trace-events
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PULL 00/36] target-arm queue
2020-12-10 11:47 Peter Maydell
@ 2020-12-10 12:51 ` Peter Maydell
0 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2020-12-10 12:51 UTC (permalink / raw)
To: QEMU Developers
On Thu, 10 Dec 2020 at 11:47, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> First pullreq for 6.0: mostly my v8.1M work, plus some other
> bits and pieces. (I still have a lot of stuff in my to-review
> folder, which I may or may not get to before the Christmas break...)
>
> thanks
> -- PMM
>
> The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210
>
> for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
>
> hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/smmuv3: Fix up L1STD_SPAN decoding
> * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
> * sbsa-ref: allow to use Cortex-A53/57/72 cpus
> * Various minor code cleanups
> * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
> * Implement more pieces of ARMv8.1M support
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PULL 00/36] target-arm queue
@ 2024-01-26 14:33 Peter Maydell
2024-01-26 14:33 ` [PULL 01/36] target/xtensa: fix OOB TLB entry access Peter Maydell
` (36 more replies)
0 siblings, 37 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 5bab95dc74d43bbb28c6a96d24c810a664432057:
Merge tag 'pull-request-2024-01-24' of https://gitlab.com/thuth/qemu into staging (2024-01-25 12:33:42 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240126
for you to fetch changes up to 5e6be95ed1578c7cfac2082b39384d99fd912508:
hw/arm: add PCIe to Freescale i.MX6 (2024-01-26 12:23:04 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix VNCR fault detection logic
* Fix A64 scalar SQSHRN and SQRSHRN
* Fix incorrect aa64_tidcp1 feature check
* hw/arm/virt.c: Remove newline from error_report() string
* hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
* hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
* hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
* hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
* hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
* hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
* arm: various include header cleanups
* cleanups to allow some files to be built only once
* fsl-imx6ul: Add various missing unimplemented devices
* docs/system/arm/virt.rst: Add note on CPU features off by default
* hw/char/imx_serial: Implement receive FIFO and ageing timer
* target/xtensa: fix OOB TLB entry access
* bswap.h: Fix const_le64() macro
* hw/arm: add PCIe to Freescale i.MX6
----------------------------------------------------------------
Guenter Roeck (4):
hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
fsl-imx6ul: Add various missing unimplemented devices
Gustavo Romero (1):
docs/system/arm/virt.rst: Add note on CPU features off by default
Max Filippov (1):
target/xtensa: fix OOB TLB entry access
Nikita Ostrenkov (1):
hw/arm: add PCIe to Freescale i.MX6
Peter Maydell (6):
target/arm: Fix VNCR fault detection logic
hw/arm/virt.c: Remove newline from error_report() string
hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
target/arm: Fix A64 scalar SQSHRN and SQRSHRN
bswap.h: Fix const_le64() macro
target/arm: Fix incorrect aa64_tidcp1 feature check
Philippe Mathieu-Daudé (20):
hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
hw/arm/exynos4210: Include missing 'exec/tswap.h' header
hw/arm/xilinx_zynq: Include missing 'exec/tswap.h' header
hw/arm/smmuv3: Include missing 'hw/registerfields.h' header
hw/arm/xlnx-versal: Include missing 'cpu.h' header
target/arm/cpu-features: Include missing 'hw/registerfields.h' header
target/arm/cpregs: Include missing 'hw/registerfields.h' header
target/arm/cpregs: Include missing 'kvm-consts.h' header
target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
hw/cpu/a9mpcore: Build it only once
hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'
hw/misc/xlnx-versal-crl: Build it only once
target/arm: Expose M-profile register bank index definitions
hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header
target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
target/arm: Move e2h_access() helper around
target/arm: Move GTimer definitions to new 'gtimer.h' header
hw/arm: Build various units only once
Rayhan Faizel (1):
hw/char/imx_serial: Implement receive FIFO and ageing timer
Richard Henderson (2):
target/arm: Rename arm_cpu_mp_affinity
target/arm: Create arm_cpu_mp_affinity
docs/system/arm/bananapi_m2u.rst | 5 +-
docs/system/arm/virt.rst | 13 ++++
hw/arm/smmuv3-internal.h | 1 +
include/hw/arm/allwinner-r40.h | 15 +++++
include/hw/arm/fsl-imx6.h | 44 +++++++------
include/hw/arm/fsl-imx6ul.h | 2 +
include/hw/arm/xlnx-versal.h | 1 +
include/hw/char/imx_serial.h | 20 +++++-
include/hw/intc/armv7m_nvic.h | 2 +-
include/hw/misc/xlnx-versal-crl.h | 2 +-
include/qemu/bswap.h | 16 ++---
target/arm/cpregs.h | 3 +
target/arm/cpu-features.h | 4 +-
target/arm/cpu-qom.h | 24 +++++++
target/arm/cpu.h | 34 +---------
target/arm/gtimer.h | 21 ++++++
target/arm/multiprocessing.h | 16 +++++
hw/arm/allwinner-a10.c | 50 ++++++--------
hw/arm/allwinner-h3.c | 2 +
hw/arm/allwinner-r40.c | 69 +++++++++++++++++++-
hw/arm/armv7m.c | 2 +
hw/arm/aspeed_ast2400.c | 1 +
hw/arm/aspeed_ast2600.c | 1 +
hw/arm/bcm2836.c | 2 +
hw/arm/collie.c | 1 -
hw/arm/exynos4210.c | 2 +
hw/arm/fsl-imx25.c | 1 +
hw/arm/fsl-imx31.c | 1 +
hw/arm/fsl-imx6.c | 26 ++++++++
hw/arm/fsl-imx6ul.c | 31 +++++++++
hw/arm/fsl-imx7.c | 1 +
hw/arm/gumstix.c | 1 -
hw/arm/highbank.c | 1 +
hw/arm/integratorcp.c | 2 +-
hw/arm/mainstone.c | 1 -
hw/arm/musicpal.c | 133 ++++++++++++++++++--------------------
hw/arm/npcm7xx.c | 3 +-
hw/arm/nseries.c | 4 +-
hw/arm/omap1.c | 1 +
hw/arm/omap2.c | 2 +-
hw/arm/omap_sx1.c | 1 -
hw/arm/palm.c | 1 -
hw/arm/realview.c | 1 +
hw/arm/sbsa-ref.c | 4 +-
hw/arm/spitz.c | 1 -
hw/arm/strongarm.c | 2 +-
hw/arm/versatilepb.c | 2 +-
hw/arm/vexpress.c | 2 +-
hw/arm/virt-acpi-build.c | 4 +-
hw/arm/virt.c | 15 +++--
hw/arm/xilinx_zynq.c | 3 +-
hw/arm/xlnx-versal-virt.c | 5 +-
hw/arm/xlnx-versal.c | 2 +
hw/arm/xlnx-zynqmp.c | 2 +
hw/arm/z2.c | 1 -
hw/char/imx_serial.c | 102 +++++++++++++++++++++++++----
hw/cpu/a15mpcore.c | 1 +
hw/cpu/a9mpcore.c | 2 +-
hw/misc/xlnx-versal-crl.c | 5 +-
target/arm/arm-powerctl.c | 3 +-
target/arm/cpu.c | 13 +++-
target/arm/helper.c | 30 +++++----
target/arm/hvf/hvf.c | 6 +-
target/arm/kvm.c | 1 +
target/arm/machine.c | 1 +
target/arm/tcg/psci.c | 3 +-
target/arm/tcg/tlb_helper.c | 2 +-
target/arm/tcg/translate-a64.c | 2 +-
target/xtensa/mmu_helper.c | 47 ++++++++++----
hw/arm/Kconfig | 6 ++
hw/arm/meson.build | 23 +++----
hw/cpu/meson.build | 2 +-
hw/misc/meson.build | 2 +-
73 files changed, 597 insertions(+), 261 deletions(-)
create mode 100644 target/arm/gtimer.h
create mode 100644 target/arm/multiprocessing.h
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PULL 01/36] target/xtensa: fix OOB TLB entry access
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 02/36] target/arm: Fix VNCR fault detection logic Peter Maydell
` (35 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Max Filippov <jcmvbkbc@gmail.com>
r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register
by the guest. The host uses 3 bits of the index for ITLB indexing and 4
bits for DTLB, but there's only 7 entries in the ITLB array and 10 in
the DTLB array, so a malicious guest may trigger out-of-bound access to
these arrays.
Change split_tlb_entry_spec return type to bool to indicate whether TLB
way passed to it is valid. Change get_tlb_entry to return NULL in case
invalid TLB way is requested. Add assertion to xtensa_tlb_get_entry that
requested TLB way and entry indices are valid. Add checks to the
[rwi]tlb helpers that requested TLB way is valid and return 0 or do
nothing when it's not.
Cc: qemu-stable@nongnu.org
Fixes: b67ea0cd7441 ("target-xtensa: implement memory protection options")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20231215120307.545381-1-jcmvbkbc@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/xtensa/mmu_helper.c | 47 ++++++++++++++++++++++++++++----------
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 12552a33470..2fda4e887cc 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -224,22 +224,31 @@ static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v,
* Split TLB address into TLB way, entry index and VPN (with index).
* See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
*/
-static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
- uint32_t *vpn, uint32_t *wi, uint32_t *ei)
+static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
+ uint32_t *vpn, uint32_t *wi, uint32_t *ei)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
*wi = v & (dtlb ? 0xf : 0x7);
- split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
+ if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) {
+ split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
+ return true;
+ } else {
+ return false;
+ }
} else {
*vpn = v & REGION_PAGE_MASK;
*wi = 0;
*ei = (v >> 29) & 0x7;
+ return true;
}
}
static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei)
{
+ const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb;
+
+ assert(wi < tlb->nways && ei < tlb->way_size[wi]);
return dtlb ?
env->dtlb[wi] + ei :
env->itlb[wi] + ei;
@@ -252,11 +261,14 @@ static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
uint32_t wi;
uint32_t ei;
- split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
- if (pwi) {
- *pwi = wi;
+ if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
+ if (pwi) {
+ *pwi = wi;
+ }
+ return xtensa_tlb_get_entry(env, dtlb, wi, ei);
+ } else {
+ return NULL;
}
- return xtensa_tlb_get_entry(env, dtlb, wi, ei);
}
static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
@@ -482,7 +494,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
- return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
+
+ if (entry) {
+ return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
+ } else {
+ return 0;
+ }
} else {
return v & REGION_PAGE_MASK;
}
@@ -491,7 +508,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
- return entry->paddr | entry->attr;
+
+ if (entry) {
+ return entry->paddr | entry->attr;
+ } else {
+ return 0;
+ }
}
void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
@@ -499,7 +521,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
- if (entry->variable && entry->asid) {
+ if (entry && entry->variable && entry->asid) {
tlb_flush_page(env_cpu(env), entry->vaddr);
entry->asid = 0;
}
@@ -537,8 +559,9 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
uint32_t vpn;
uint32_t wi;
uint32_t ei;
- split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
- xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
+ if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
+ xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
+ }
}
/*!
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 02/36] target/arm: Fix VNCR fault detection logic
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
2024-01-26 14:33 ` [PULL 01/36] target/xtensa: fix OOB TLB entry access Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 03/36] hw/arm/virt.c: Remove newline from error_report() string Peter Maydell
` (34 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
In arm_deliver_fault() we check for whether the fault is caused
by a data abort due to an access to a FEAT_NV2 sysreg in the
memory pointed to by the VNCR. Unfortunately part of the
condition checks the wrong argument to the function, meaning
that it would spuriously trigger, resulting in some instruction
aborts being taken to the wrong EL and reported incorrectly.
Use the right variable in the condition.
Fixes: 674e5345275d425 ("target/arm: Report VNCR_EL2 based faults correctly")
Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-id: 20240116165605.2523055-1-peter.maydell@linaro.org
---
target/arm/tcg/tlb_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index dd5de74ffb7..5477c7fb7dc 100644
--- a/target/arm/tcg/tlb_helper.c
+++ b/target/arm/tcg/tlb_helper.c
@@ -184,7 +184,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
* (and indeed syndrome does not have the EC field in it,
* because we masked that out in disas_set_insn_syndrome())
*/
- bool is_vncr = (mmu_idx != MMU_INST_FETCH) &&
+ bool is_vncr = (access_type != MMU_INST_FETCH) &&
(env->exception.syndrome & ARM_EL_VNCR);
if (is_vncr) {
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 03/36] hw/arm/virt.c: Remove newline from error_report() string
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
2024-01-26 14:33 ` [PULL 01/36] target/xtensa: fix OOB TLB entry access Peter Maydell
2024-01-26 14:33 ` [PULL 02/36] target/arm: Fix VNCR fault detection logic Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 04/36] hw/arm/musicpal: Convert to qemu_add_kbd_event_handler() Peter Maydell
` (33 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
error_report() strings should not include trailing newlines; remove
the newline from the error we print when devices won't fit into the
address space of the CPU.
This commit also fixes the accidental hardcoded tabs that were in
this line, since we have to touch the line anyway.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240118131649.2726375-1-peter.maydell@linaro.org
---
hw/arm/virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 5cbc69dff83..ed4ed9f4142 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1771,8 +1771,8 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
/* Base address of the high IO region */
memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
if (memtop > BIT_ULL(pa_bits)) {
- error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
- pa_bits, memtop - BIT_ULL(pa_bits));
+ error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
+ pa_bits, memtop - BIT_ULL(pa_bits));
exit(EXIT_FAILURE);
}
if (base < device_memory_base) {
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 04/36] hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2024-01-26 14:33 ` [PULL 03/36] hw/arm/virt.c: Remove newline from error_report() string Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 05/36] hw/arm/allwinner-a10: Unconditionally map the USB Host controllers Peter Maydell
` (32 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
Convert the musicpal key input device to use
qemu_add_kbd_event_handler(). This lets us simplify it because we no
longer need to track whether we're in the middle of a PS/2 multibyte
key sequence.
In the conversion we move the keyboard handler registration from init
to realize, because devices shouldn't disturb the state of the
simulation by doing things like registering input handlers until
they're realized, so that device objects can be introspected
safely.
The behaviour where key-repeat is permitted for the arrow-keys only
is intentional (added in commit 7c6ce4baedfcd0c), so we retain it,
and add a comment to that effect.
This is a migration compatibility break for musicpal.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20231103182750.855577-1-peter.maydell@linaro.org
---
hw/arm/musicpal.c | 131 +++++++++++++++++++++-------------------------
1 file changed, 61 insertions(+), 70 deletions(-)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 3200c9f68ac..6987472871e 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1043,20 +1043,6 @@ static const TypeInfo musicpal_gpio_info = {
};
/* Keyboard codes & masks */
-#define KEY_RELEASED 0x80
-#define KEY_CODE 0x7f
-
-#define KEYCODE_TAB 0x0f
-#define KEYCODE_ENTER 0x1c
-#define KEYCODE_F 0x21
-#define KEYCODE_M 0x32
-
-#define KEYCODE_EXTENDED 0xe0
-#define KEYCODE_UP 0x48
-#define KEYCODE_DOWN 0x50
-#define KEYCODE_LEFT 0x4b
-#define KEYCODE_RIGHT 0x4d
-
#define MP_KEY_WHEEL_VOL (1 << 0)
#define MP_KEY_WHEEL_VOL_INV (1 << 1)
#define MP_KEY_WHEEL_NAV (1 << 2)
@@ -1074,67 +1060,66 @@ struct musicpal_key_state {
SysBusDevice parent_obj;
/*< public >*/
- uint32_t kbd_extended;
uint32_t pressed_keys;
qemu_irq out[8];
};
-static void musicpal_key_event(void *opaque, int keycode)
+static void musicpal_key_event(DeviceState *dev, QemuConsole *src,
+ InputEvent *evt)
{
- musicpal_key_state *s = opaque;
+ musicpal_key_state *s = MUSICPAL_KEY(dev);
+ InputKeyEvent *key = evt->u.key.data;
+ int qcode = qemu_input_key_value_to_qcode(key->key);
uint32_t event = 0;
int i;
- if (keycode == KEYCODE_EXTENDED) {
- s->kbd_extended = 1;
- return;
+ switch (qcode) {
+ case Q_KEY_CODE_UP:
+ event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
+ break;
+
+ case Q_KEY_CODE_DOWN:
+ event = MP_KEY_WHEEL_NAV;
+ break;
+
+ case Q_KEY_CODE_LEFT:
+ event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
+ break;
+
+ case Q_KEY_CODE_RIGHT:
+ event = MP_KEY_WHEEL_VOL;
+ break;
+
+ case Q_KEY_CODE_F:
+ event = MP_KEY_BTN_FAVORITS;
+ break;
+
+ case Q_KEY_CODE_TAB:
+ event = MP_KEY_BTN_VOLUME;
+ break;
+
+ case Q_KEY_CODE_RET:
+ event = MP_KEY_BTN_NAVIGATION;
+ break;
+
+ case Q_KEY_CODE_M:
+ event = MP_KEY_BTN_MENU;
+ break;
}
- if (s->kbd_extended) {
- switch (keycode & KEY_CODE) {
- case KEYCODE_UP:
- event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
- break;
-
- case KEYCODE_DOWN:
- event = MP_KEY_WHEEL_NAV;
- break;
-
- case KEYCODE_LEFT:
- event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
- break;
-
- case KEYCODE_RIGHT:
- event = MP_KEY_WHEEL_VOL;
- break;
- }
- } else {
- switch (keycode & KEY_CODE) {
- case KEYCODE_F:
- event = MP_KEY_BTN_FAVORITS;
- break;
-
- case KEYCODE_TAB:
- event = MP_KEY_BTN_VOLUME;
- break;
-
- case KEYCODE_ENTER:
- event = MP_KEY_BTN_NAVIGATION;
- break;
-
- case KEYCODE_M:
- event = MP_KEY_BTN_MENU;
- break;
- }
- /* Do not repeat already pressed buttons */
- if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
+ /*
+ * We allow repeated wheel-events when the arrow keys are held down,
+ * but do not repeat already-pressed buttons for the other key inputs.
+ */
+ if (!(event & (MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_VOL))) {
+ if (key->down && (s->pressed_keys & event)) {
event = 0;
}
}
if (event) {
/* Raise GPIO pin first if repeating a key */
- if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
+ if (key->down && (s->pressed_keys & event)) {
for (i = 0; i <= 7; i++) {
if (event & (1 << i)) {
qemu_set_irq(s->out[i], 1);
@@ -1143,17 +1128,15 @@ static void musicpal_key_event(void *opaque, int keycode)
}
for (i = 0; i <= 7; i++) {
if (event & (1 << i)) {
- qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
+ qemu_set_irq(s->out[i], !key->down);
}
}
- if (keycode & KEY_RELEASED) {
- s->pressed_keys &= ~event;
- } else {
+ if (key->down) {
s->pressed_keys |= event;
+ } else {
+ s->pressed_keys &= ~event;
}
}
-
- s->kbd_extended = 0;
}
static void musicpal_key_init(Object *obj)
@@ -1162,20 +1145,27 @@ static void musicpal_key_init(Object *obj)
DeviceState *dev = DEVICE(sbd);
musicpal_key_state *s = MUSICPAL_KEY(dev);
- s->kbd_extended = 0;
s->pressed_keys = 0;
qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out));
+}
- qemu_add_kbd_event_handler(musicpal_key_event, s);
+static const QemuInputHandler musicpal_key_handler = {
+ .name = "musicpal_key",
+ .mask = INPUT_EVENT_MASK_KEY,
+ .event = musicpal_key_event,
+};
+
+static void musicpal_key_realize(DeviceState *dev, Error **errp)
+{
+ qemu_input_handler_register(dev, &musicpal_key_handler);
}
static const VMStateDescription musicpal_key_vmsd = {
.name = "musicpal_key",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (const VMStateField[]) {
- VMSTATE_UINT32(kbd_extended, musicpal_key_state),
VMSTATE_UINT32(pressed_keys, musicpal_key_state),
VMSTATE_END_OF_LIST()
}
@@ -1186,6 +1176,7 @@ static void musicpal_key_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &musicpal_key_vmsd;
+ dc->realize = musicpal_key_realize;
}
static const TypeInfo musicpal_key_info = {
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 05/36] hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2024-01-26 14:33 ` [PULL 04/36] hw/arm/musicpal: Convert to qemu_add_kbd_event_handler() Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 06/36] hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller Peter Maydell
` (31 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The USB Controllers are part of the chipset, thus are
always present and mapped in memory.
This is a migration compatibility break for the cubieboard
machine started with the '-usb none' option.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20240119215106.45776-2-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/allwinner-a10.c | 49 +++++++++++++++++-------------------------
1 file changed, 20 insertions(+), 29 deletions(-)
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index b0ea3f7f662..0135632996c 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -79,15 +79,10 @@ static void aw_a10_init(Object *obj)
object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
- if (machine_usb(current_machine)) {
- int i;
-
- for (i = 0; i < AW_A10_NUM_USB; i++) {
- object_initialize_child(obj, "ehci[*]", &s->ehci[i],
- TYPE_PLATFORM_EHCI);
- object_initialize_child(obj, "ohci[*]", &s->ohci[i],
- TYPE_SYSBUS_OHCI);
- }
+ for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i],
+ TYPE_PLATFORM_EHCI);
+ object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
}
object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
@@ -165,28 +160,24 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(dev, 1),
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
- if (machine_usb(current_machine)) {
- int i;
+ for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
+ g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
- for (i = 0; i < AW_A10_NUM_USB; i++) {
- g_autofree char *bus = g_strdup_printf("usb-bus.%d", i);
+ object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
+ true, &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ AW_A10_EHCI_BASE + i * 0x8000);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ qdev_get_gpio_in(dev, 39 + i));
- object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
- true, &error_fatal);
- sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
- AW_A10_EHCI_BASE + i * 0x8000);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
- qdev_get_gpio_in(dev, 39 + i));
-
- object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
- &error_fatal);
- sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
- AW_A10_OHCI_BASE + i * 0x8000);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
- qdev_get_gpio_in(dev, 64 + i));
- }
+ object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
+ &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
+ AW_A10_OHCI_BASE + i * 0x8000);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
+ qdev_get_gpio_in(dev, 64 + i));
}
/* SD/MMC */
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 06/36] hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2024-01-26 14:33 ` [PULL 05/36] hw/arm/allwinner-a10: Unconditionally map the USB Host controllers Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 07/36] hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board Peter Maydell
` (30 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The TUSB6010 USB controller is soldered on the N800 and N810
tablets, thus is always present.
This is a migration compatibility break for the n800/n810
machines started with the '-usb none' option.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240119215106.45776-3-philmd@linaro.org
[PMM: fixed commit message typo]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/nseries.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index 35aff46b4b4..35deb74f655 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -1353,9 +1353,7 @@ static void n8x0_init(MachineState *machine,
n8x0_spi_setup(s);
n8x0_dss_setup(s);
n8x0_cbus_setup(s);
- if (machine_usb(machine)) {
- n8x0_usb_setup(s);
- }
+ n8x0_usb_setup(s);
if (machine->kernel_filename) {
/* Or at the linux loader. */
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 07/36] hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2024-01-26 14:33 ` [PULL 06/36] hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 08/36] hw/arm: Add AHCI/SATA controller " Peter Maydell
` (29 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Guenter Roeck <linux@roeck-us.net>
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machine USB support is not enabled, create unimplemented devices
for the USB memory ranges to avoid crashes when booting Linux.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240115182757.1095012-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/bananapi_m2u.rst | 2 +-
include/hw/arm/allwinner-r40.h | 9 ++++++
hw/arm/allwinner-r40.c | 47 ++++++++++++++++++++++++++++++--
hw/arm/Kconfig | 2 ++
4 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/bananapi_m2u.rst b/docs/system/arm/bananapi_m2u.rst
index b09ba5c5486..e77c425e2cb 100644
--- a/docs/system/arm/bananapi_m2u.rst
+++ b/docs/system/arm/bananapi_m2u.rst
@@ -23,6 +23,7 @@ The Banana Pi M2U machine supports the following devices:
* GMAC ethernet
* Clock Control Unit
* TWI (I2C)
+ * USB 2.0
Limitations
"""""""""""
@@ -33,7 +34,6 @@ Currently, Banana Pi M2U does *not* support the following features:
- Audio output
- Hardware Watchdog
- Real Time Clock
-- USB 2.0 interfaces
Also see the 'unimplemented' array in the Allwinner R40 SoC module
for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-r40.c``
diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h
index 6e1ac9d4c13..ae82822d424 100644
--- a/include/hw/arm/allwinner-r40.h
+++ b/include/hw/arm/allwinner-r40.h
@@ -30,6 +30,8 @@
#include "hw/i2c/allwinner-i2c.h"
#include "hw/net/allwinner_emac.h"
#include "hw/net/allwinner-sun8i-emac.h"
+#include "hw/usb/hcd-ohci.h"
+#include "hw/usb/hcd-ehci.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@@ -44,6 +46,10 @@ enum {
AW_R40_DEV_MMC1,
AW_R40_DEV_MMC2,
AW_R40_DEV_MMC3,
+ AW_R40_DEV_EHCI1,
+ AW_R40_DEV_OHCI1,
+ AW_R40_DEV_EHCI2,
+ AW_R40_DEV_OHCI2,
AW_R40_DEV_CCU,
AW_R40_DEV_PIT,
AW_R40_DEV_UART0,
@@ -88,6 +94,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
* which are currently emulated by the R40 SoC code.
*/
#define AW_R40_NUM_MMCS 4
+#define AW_R40_NUM_USB 2
#define AW_R40_NUM_UARTS 8
struct AwR40State {
@@ -106,6 +113,8 @@ struct AwR40State {
AwSRAMCState sramc;
AwA10PITState timer;
AwSdHostState mmc[AW_R40_NUM_MMCS];
+ EHCISysBusState ehci[AW_R40_NUM_USB];
+ OHCISysBusState ohci[AW_R40_NUM_USB];
AwR40ClockCtlState ccu;
AwR40DramCtlState dramc;
AWI2CState i2c0;
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
index a0d367c60d1..2e8943eff74 100644
--- a/hw/arm/allwinner-r40.c
+++ b/hw/arm/allwinner-r40.c
@@ -23,6 +23,7 @@
#include "qemu/bswap.h"
#include "qemu/module.h"
#include "qemu/units.h"
+#include "hw/boards.h"
#include "hw/qdev-core.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
@@ -45,6 +46,10 @@ const hwaddr allwinner_r40_memmap[] = {
[AW_R40_DEV_MMC1] = 0x01c10000,
[AW_R40_DEV_MMC2] = 0x01c11000,
[AW_R40_DEV_MMC3] = 0x01c12000,
+ [AW_R40_DEV_EHCI1] = 0x01c19000,
+ [AW_R40_DEV_OHCI1] = 0x01c19400,
+ [AW_R40_DEV_EHCI2] = 0x01c1c000,
+ [AW_R40_DEV_OHCI2] = 0x01c1c400,
[AW_R40_DEV_CCU] = 0x01c20000,
[AW_R40_DEV_PIT] = 0x01c20c00,
[AW_R40_DEV_UART0] = 0x01c28000,
@@ -89,9 +94,9 @@ static struct AwR40Unimplemented r40_unimplemented[] = {
{ "crypto", 0x01c15000, 4 * KiB },
{ "spi2", 0x01c17000, 4 * KiB },
{ "sata", 0x01c18000, 4 * KiB },
- { "usb1-host", 0x01c19000, 4 * KiB },
+ { "usb1-phy", 0x01c19800, 2 * KiB },
{ "sid", 0x01c1b000, 4 * KiB },
- { "usb2-host", 0x01c1c000, 4 * KiB },
+ { "usb2-phy", 0x01c1c800, 2 * KiB },
{ "cs1", 0x01c1d000, 4 * KiB },
{ "spi3", 0x01c1f000, 4 * KiB },
{ "rtc", 0x01c20400, 1 * KiB },
@@ -181,6 +186,10 @@ enum {
AW_R40_GIC_SPI_MMC2 = 34,
AW_R40_GIC_SPI_MMC3 = 35,
AW_R40_GIC_SPI_EMAC = 55,
+ AW_R40_GIC_SPI_OHCI1 = 64,
+ AW_R40_GIC_SPI_OHCI2 = 65,
+ AW_R40_GIC_SPI_EHCI1 = 76,
+ AW_R40_GIC_SPI_EHCI2 = 78,
AW_R40_GIC_SPI_GMAC = 85,
};
@@ -276,6 +285,13 @@ static void allwinner_r40_init(Object *obj)
TYPE_AW_SDHOST_SUN50I_A64);
}
+ for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i],
+ TYPE_PLATFORM_EHCI);
+ object_initialize_child(obj, "ohci[*]", &s->ohci[i],
+ TYPE_SYSBUS_OHCI);
+ }
+
object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
@@ -407,6 +423,33 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
+ /* USB */
+ for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
+ g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
+
+ object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true,
+ &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2
+ : AW_R40_DEV_EHCI1]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ i ? AW_R40_GIC_SPI_EHCI2
+ : AW_R40_GIC_SPI_EHCI1));
+
+ object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
+ &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
+ allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2
+ : AW_R40_DEV_OHCI1]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ i ? AW_R40_GIC_SPI_OHCI2
+ : AW_R40_GIC_SPI_OHCI1));
+ }
+
/* SD/MMC */
for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 218b454e97f..4a2a5fca974 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -415,6 +415,8 @@ config ALLWINNER_R40
select ARM_TIMER
select ARM_GIC
select UNIMP
+ select USB_OHCI
+ select USB_EHCI_SYSBUS
select SD
config RASPI
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 08/36] hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2024-01-26 14:33 ` [PULL 07/36] hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 09/36] hw/arm: Add watchdog timer to Allwinner H40 " Peter Maydell
` (28 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Guenter Roeck <linux@roeck-us.net>
Allwinner R40 supports an AHCI compliant SATA controller.
Add support for it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20240115182757.1095012-3-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/bananapi_m2u.rst | 1 +
include/hw/arm/allwinner-r40.h | 3 +++
hw/arm/allwinner-r40.c | 12 +++++++++++-
hw/arm/Kconfig | 1 +
4 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/bananapi_m2u.rst b/docs/system/arm/bananapi_m2u.rst
index e77c425e2cb..542310591d6 100644
--- a/docs/system/arm/bananapi_m2u.rst
+++ b/docs/system/arm/bananapi_m2u.rst
@@ -22,6 +22,7 @@ The Banana Pi M2U machine supports the following devices:
* EMAC ethernet
* GMAC ethernet
* Clock Control Unit
+ * SATA
* TWI (I2C)
* USB 2.0
diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h
index ae82822d424..c589fcc1c15 100644
--- a/include/hw/arm/allwinner-r40.h
+++ b/include/hw/arm/allwinner-r40.h
@@ -22,6 +22,7 @@
#include "qom/object.h"
#include "hw/timer/allwinner-a10-pit.h"
+#include "hw/ide/ahci.h"
#include "hw/intc/arm_gic.h"
#include "hw/sd/allwinner-sdhost.h"
#include "hw/misc/allwinner-r40-ccu.h"
@@ -46,6 +47,7 @@ enum {
AW_R40_DEV_MMC1,
AW_R40_DEV_MMC2,
AW_R40_DEV_MMC3,
+ AW_R40_DEV_AHCI,
AW_R40_DEV_EHCI1,
AW_R40_DEV_OHCI1,
AW_R40_DEV_EHCI2,
@@ -112,6 +114,7 @@ struct AwR40State {
const hwaddr *memmap;
AwSRAMCState sramc;
AwA10PITState timer;
+ AllwinnerAHCIState sata;
AwSdHostState mmc[AW_R40_NUM_MMCS];
EHCISysBusState ehci[AW_R40_NUM_USB];
OHCISysBusState ohci[AW_R40_NUM_USB];
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
index 2e8943eff74..534be4a735d 100644
--- a/hw/arm/allwinner-r40.c
+++ b/hw/arm/allwinner-r40.c
@@ -46,6 +46,7 @@ const hwaddr allwinner_r40_memmap[] = {
[AW_R40_DEV_MMC1] = 0x01c10000,
[AW_R40_DEV_MMC2] = 0x01c11000,
[AW_R40_DEV_MMC3] = 0x01c12000,
+ [AW_R40_DEV_AHCI] = 0x01c18000,
[AW_R40_DEV_EHCI1] = 0x01c19000,
[AW_R40_DEV_OHCI1] = 0x01c19400,
[AW_R40_DEV_EHCI2] = 0x01c1c000,
@@ -93,7 +94,6 @@ static struct AwR40Unimplemented r40_unimplemented[] = {
{ "usb0-host", 0x01c14000, 4 * KiB },
{ "crypto", 0x01c15000, 4 * KiB },
{ "spi2", 0x01c17000, 4 * KiB },
- { "sata", 0x01c18000, 4 * KiB },
{ "usb1-phy", 0x01c19800, 2 * KiB },
{ "sid", 0x01c1b000, 4 * KiB },
{ "usb2-phy", 0x01c1c800, 2 * KiB },
@@ -186,6 +186,7 @@ enum {
AW_R40_GIC_SPI_MMC2 = 34,
AW_R40_GIC_SPI_MMC3 = 35,
AW_R40_GIC_SPI_EMAC = 55,
+ AW_R40_GIC_SPI_AHCI = 56,
AW_R40_GIC_SPI_OHCI1 = 64,
AW_R40_GIC_SPI_OHCI2 = 65,
AW_R40_GIC_SPI_EHCI1 = 76,
@@ -285,6 +286,8 @@ static void allwinner_r40_init(Object *obj)
TYPE_AW_SDHOST_SUN50I_A64);
}
+ object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
+
for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
@@ -423,6 +426,13 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
+ /* SATA / AHCI */
+ sysbus_realize(SYS_BUS_DEVICE(&s->sata), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0,
+ allwinner_r40_memmap[AW_R40_DEV_AHCI]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_AHCI));
+
/* USB */
for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 4a2a5fca974..704517edd4f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -408,6 +408,7 @@ config ALLWINNER_H3
config ALLWINNER_R40
bool
default y if TCG && ARM
+ select AHCI
select ALLWINNER_SRAMC
select ALLWINNER_A10_PIT
select AXP2XX_PMU
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 09/36] hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2024-01-26 14:33 ` [PULL 08/36] hw/arm: Add AHCI/SATA controller " Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 10/36] hw/arm/exynos4210: Include missing 'exec/tswap.h' header Peter Maydell
` (27 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Guenter Roeck <linux@roeck-us.net>
Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Message-id: 20240115182757.1095012-4-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/bananapi_m2u.rst | 2 +-
include/hw/arm/allwinner-r40.h | 3 +++
hw/arm/allwinner-r40.c | 8 ++++++++
hw/arm/Kconfig | 1 +
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/bananapi_m2u.rst b/docs/system/arm/bananapi_m2u.rst
index 542310591d6..587b4886553 100644
--- a/docs/system/arm/bananapi_m2u.rst
+++ b/docs/system/arm/bananapi_m2u.rst
@@ -25,6 +25,7 @@ The Banana Pi M2U machine supports the following devices:
* SATA
* TWI (I2C)
* USB 2.0
+ * Hardware Watchdog
Limitations
"""""""""""
@@ -33,7 +34,6 @@ Currently, Banana Pi M2U does *not* support the following features:
- Graphical output via HDMI, GPU and/or the Display Engine
- Audio output
-- Hardware Watchdog
- Real Time Clock
Also see the 'unimplemented' array in the Allwinner R40 SoC module
diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h
index c589fcc1c15..66c38e7d907 100644
--- a/include/hw/arm/allwinner-r40.h
+++ b/include/hw/arm/allwinner-r40.h
@@ -33,6 +33,7 @@
#include "hw/net/allwinner-sun8i-emac.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
+#include "hw/watchdog/allwinner-wdt.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@@ -54,6 +55,7 @@ enum {
AW_R40_DEV_OHCI2,
AW_R40_DEV_CCU,
AW_R40_DEV_PIT,
+ AW_R40_DEV_WDT,
AW_R40_DEV_UART0,
AW_R40_DEV_UART1,
AW_R40_DEV_UART2,
@@ -114,6 +116,7 @@ struct AwR40State {
const hwaddr *memmap;
AwSRAMCState sramc;
AwA10PITState timer;
+ AwWdtState wdt;
AllwinnerAHCIState sata;
AwSdHostState mmc[AW_R40_NUM_MMCS];
EHCISysBusState ehci[AW_R40_NUM_USB];
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
index 534be4a735d..a28e5b3886a 100644
--- a/hw/arm/allwinner-r40.c
+++ b/hw/arm/allwinner-r40.c
@@ -53,6 +53,7 @@ const hwaddr allwinner_r40_memmap[] = {
[AW_R40_DEV_OHCI2] = 0x01c1c400,
[AW_R40_DEV_CCU] = 0x01c20000,
[AW_R40_DEV_PIT] = 0x01c20c00,
+ [AW_R40_DEV_WDT] = 0x01c20c90,
[AW_R40_DEV_UART0] = 0x01c28000,
[AW_R40_DEV_UART1] = 0x01c28400,
[AW_R40_DEV_UART2] = 0x01c28800,
@@ -279,6 +280,8 @@ static void allwinner_r40_init(Object *obj)
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
"clk1-freq");
+ object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
+
object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU);
for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
@@ -545,6 +548,11 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC));
+ /* WDT */
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
+ allwinner_r40_memmap[AW_R40_DEV_WDT], 1);
+
/* Unimplemented devices */
for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
create_unimplemented_device(r40_unimplemented[i].device_name,
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 704517edd4f..2bc3ea3425e 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -411,6 +411,7 @@ config ALLWINNER_R40
select AHCI
select ALLWINNER_SRAMC
select ALLWINNER_A10_PIT
+ select ALLWINNER_WDT
select AXP2XX_PMU
select SERIAL
select ARM_TIMER
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 10/36] hw/arm/exynos4210: Include missing 'exec/tswap.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2024-01-26 14:33 ` [PULL 09/36] hw/arm: Add watchdog timer to Allwinner H40 " Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 11/36] hw/arm/xilinx_zynq: " Peter Maydell
` (26 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/arm/exynos4210.c calls tswap32() which is declared
in "exec/tswap.h". Include it in order to avoid when
refactoring unrelated headers:
hw/arm/exynos4210.c:499:22: error: call to undeclared function 'tswap32';
ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
smpboot[n] = tswap32(smpboot[n]);
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/exynos4210.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index de39fb0ece8..af511a153dd 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -23,6 +23,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "exec/tswap.h"
#include "cpu.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/irq.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 11/36] hw/arm/xilinx_zynq: Include missing 'exec/tswap.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2024-01-26 14:33 ` [PULL 10/36] hw/arm/exynos4210: Include missing 'exec/tswap.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 12/36] hw/arm/smmuv3: Include missing 'hw/registerfields.h' header Peter Maydell
` (25 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/arm/xilinx_zynq.c calls tswap32() which is declared
in "exec/tswap.h". Include it in order to avoid when
refactoring unrelated headers:
hw/arm/xilinx_zynq.c:103:31: error: call to undeclared function 'tswap32';
ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
board_setup_blob[n] = tswap32(board_setup_blob[n]);
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xilinx_zynq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index dbb9793aa13..d4c817ecdc0 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -37,6 +37,7 @@
#include "hw/qdev-clock.h"
#include "sysemu/reset.h"
#include "qom/object.h"
+#include "exec/tswap.h"
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 12/36] hw/arm/smmuv3: Include missing 'hw/registerfields.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2024-01-26 14:33 ` [PULL 11/36] hw/arm/xilinx_zynq: " Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 13/36] hw/arm/xlnx-versal: Include missing 'cpu.h' header Peter Maydell
` (24 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/arm/smmuv3-internal.h uses the REG32() and FIELD()
macros defined in "hw/registerfields.h". Include it in
order to avoid when refactoring unrelated headers:
In file included from ../../hw/arm/smmuv3.c:34:
hw/arm/smmuv3-internal.h:36:28: error: expected identifier
REG32(IDR0, 0x0)
^
hw/arm/smmuv3-internal.h:37:5: error: expected function body after function declarator
FIELD(IDR0, S2P, 0 , 1)
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3-internal.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 6076025ad6a..e987bc4686b 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -21,6 +21,7 @@
#ifndef HW_ARM_SMMUV3_INTERNAL_H
#define HW_ARM_SMMUV3_INTERNAL_H
+#include "hw/registerfields.h"
#include "hw/arm/smmu-common.h"
typedef enum SMMUTranslationStatus {
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 13/36] hw/arm/xlnx-versal: Include missing 'cpu.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2024-01-26 14:33 ` [PULL 12/36] hw/arm/smmuv3: Include missing 'hw/registerfields.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 14/36] target/arm/cpu-features: Include missing 'hw/registerfields.h' header Peter Maydell
` (23 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
include/hw/arm/xlnx-versal.h uses the ARMCPU structure which
is defined in the "target/arm/cpu.h" header. Include it in
order to avoid when refactoring unrelated headers:
In file included from hw/arm/xlnx-versal-virt.c:20:
include/hw/arm/xlnx-versal.h:62:23: error: array has incomplete element type 'ARMCPU' (aka 'struct ArchCPU')
ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-versal.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index b24fa64557f..025beb5532d 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -34,6 +34,7 @@
#include "hw/net/xlnx-versal-canfd.h"
#include "hw/misc/xlnx-versal-cfu.h"
#include "hw/misc/xlnx-versal-cframe-reg.h"
+#include "target/arm/cpu.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 14/36] target/arm/cpu-features: Include missing 'hw/registerfields.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2024-01-26 14:33 ` [PULL 13/36] hw/arm/xlnx-versal: Include missing 'cpu.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 15/36] target/arm/cpregs: " Peter Maydell
` (22 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
target/arm/cpu-features.h uses the FIELD_EX32() macro
defined in "hw/registerfields.h". Include it in order
to avoid when refactoring unrelated headers:
target/arm/cpu-features.h:44:12: error: call to undeclared function 'FIELD_EX32';
ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-features.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 7a590c824cf..028795ff23f 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -20,6 +20,8 @@
#ifndef TARGET_ARM_FEATURES_H
#define TARGET_ARM_FEATURES_H
+#include "hw/registerfields.h"
+
/*
* Naming convention for isar_feature functions:
* Functions which test 32-bit ID registers should have _aa32_ in
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 15/36] target/arm/cpregs: Include missing 'hw/registerfields.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2024-01-26 14:33 ` [PULL 14/36] target/arm/cpu-features: Include missing 'hw/registerfields.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 16/36] target/arm/cpregs: Include missing 'kvm-consts.h' header Peter Maydell
` (21 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
target/arm/cpregs.h uses the FIELD() macro defined in
"hw/registerfields.h". Include it in order to avoid when
refactoring unrelated headers:
target/arm/cpregs.h:347:30: error: expected identifier
FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index b6fdd0f3eb4..ca2d6006ceb 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -21,6 +21,8 @@
#ifndef TARGET_ARM_CPREGS_H
#define TARGET_ARM_CPREGS_H
+#include "hw/registerfields.h"
+
/*
* ARMCPRegInfo type field bits:
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 16/36] target/arm/cpregs: Include missing 'kvm-consts.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2024-01-26 14:33 ` [PULL 15/36] target/arm/cpregs: " Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 17/36] target/arm: Rename arm_cpu_mp_affinity Peter Maydell
` (20 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
target/arm/cpregs.h uses the CP_REG_ARCH_* definitions
from "target/arm/kvm-consts.h". Include it in order to
avoid when refactoring unrelated headers:
target/arm/cpregs.h:191:18: error: use of undeclared identifier 'CP_REG_ARCH_MASK'
if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index ca2d6006ceb..cc7c54378f4 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -22,6 +22,7 @@
#define TARGET_ARM_CPREGS_H
#include "hw/registerfields.h"
+#include "target/arm/kvm-consts.h"
/*
* ARMCPRegInfo type field bits:
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 17/36] target/arm: Rename arm_cpu_mp_affinity
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2024-01-26 14:33 ` [PULL 16/36] target/arm/cpregs: Include missing 'kvm-consts.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 18/36] target/arm: Create arm_cpu_mp_affinity Peter Maydell
` (19 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Rename to arm_build_mp_affinity. This frees up the name for
other usage, and emphasizes that the cpu object is not involved.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 2 +-
hw/arm/npcm7xx.c | 2 +-
hw/arm/sbsa-ref.c | 2 +-
hw/arm/virt.c | 2 +-
target/arm/cpu.c | 6 +++---
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ec276fcd57c..55a19e8539e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1171,7 +1171,7 @@ void arm_cpu_post_init(Object *obj);
(ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
-uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
+uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_arm_cpu;
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 15ff21d0472..7fb0a233b2d 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -474,7 +474,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
/* CPUs */
for (i = 0; i < nc->num_cpus; i++) {
object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
- arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
+ arm_build_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
&error_abort);
object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 477dca06373..b8857d1e9e4 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -148,7 +148,7 @@ static const int sbsa_ref_irqmap[] = {
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
{
uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
- return arm_cpu_mp_affinity(idx, clustersz);
+ return arm_build_mp_affinity(idx, clustersz);
}
static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ed4ed9f4142..eecde04fc77 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1676,7 +1676,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
clustersz = GICV3_TARGETLIST_BITS;
}
}
- return arm_cpu_mp_affinity(idx, clustersz);
+ return arm_build_mp_affinity(idx, clustersz);
}
static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 593695b4247..5b5af7d4e1e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1307,7 +1307,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
-uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
+uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
{
uint32_t Aff1 = idx / clustersz;
uint32_t Aff0 = idx % clustersz;
@@ -2113,8 +2113,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* so these bits always RAZ.
*/
if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
- cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
- ARM_DEFAULT_CPUS_PER_CLUSTER);
+ cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index,
+ ARM_DEFAULT_CPUS_PER_CLUSTER);
}
if (cpu->reset_hivecs) {
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 18/36] target/arm: Create arm_cpu_mp_affinity
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2024-01-26 14:33 ` [PULL 17/36] target/arm: Rename arm_cpu_mp_affinity Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 19/36] target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header Peter Maydell
` (18 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Wrapper to return the mp affinity bits from the cpu.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
hw/arm/virt-acpi-build.c | 2 +-
hw/arm/virt.c | 6 +++---
hw/arm/xlnx-versal-virt.c | 3 ++-
hw/misc/xlnx-versal-crl.c | 4 ++--
target/arm/arm-powerctl.c | 2 +-
target/arm/hvf/hvf.c | 4 ++--
target/arm/tcg/psci.c | 2 +-
8 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 55a19e8539e..d1584bdb3b5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1173,6 +1173,11 @@ void arm_cpu_post_init(Object *obj);
uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
+static inline uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
+{
+ return cpu->mp_affinity;
+}
+
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_arm_cpu;
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index a22a2f43a56..2127778c1ea 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -720,7 +720,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_int_noprefix(table_data, vgic_interrupt, 4);
build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
/* MPIDR */
- build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
+ build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8);
/* Processor Power Efficiency Class */
build_append_int_noprefix(table_data, 0, 1);
/* Reserved */
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index eecde04fc77..b3592798ea9 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -370,7 +370,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
for (cpu = 0; cpu < smp_cpus; cpu++) {
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
- if (armcpu->mp_affinity & ARM_AFF3_MASK) {
+ if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
addr_cells = 2;
break;
}
@@ -397,10 +397,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
if (addr_cells == 2) {
qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
- armcpu->mp_affinity);
+ arm_cpu_mp_affinity(armcpu));
} else {
qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
- armcpu->mp_affinity);
+ arm_cpu_mp_affinity(armcpu));
}
if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 537118224fb..841ef69df66 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -107,7 +107,8 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
qemu_fdt_add_subnode(s->fdt, name);
- qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
+ qemu_fdt_setprop_cell(s->fdt, name, "reg",
+ arm_cpu_mp_affinity(armcpu));
if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
}
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
index ac6889fcf26..9bfa9baa157 100644
--- a/hw/misc/xlnx-versal-crl.c
+++ b/hw/misc/xlnx-versal-crl.c
@@ -67,9 +67,9 @@ static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
bool rst_old, bool rst_new)
{
if (rst_new) {
- arm_set_cpu_off(armcpu->mp_affinity);
+ arm_set_cpu_off(arm_cpu_mp_affinity(armcpu));
} else {
- arm_set_cpu_on_and_reset(armcpu->mp_affinity);
+ arm_set_cpu_on_and_reset(arm_cpu_mp_affinity(armcpu));
}
}
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index 88503815659..6c86e901028 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -37,7 +37,7 @@ CPUState *arm_get_cpu_by_id(uint64_t id)
CPU_FOREACH(cpu) {
ARMCPU *armcpu = ARM_CPU(cpu);
- if (armcpu->mp_affinity == id) {
+ if (arm_cpu_mp_affinity(armcpu) == id) {
return cpu;
}
}
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index a537a5bc94c..659401e12c7 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1016,7 +1016,7 @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
static void hvf_psci_cpu_off(ARMCPU *arm_cpu)
{
- int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity);
+ int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu));
assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
}
@@ -1045,7 +1045,7 @@ static bool hvf_handle_psci_call(CPUState *cpu)
int32_t ret = 0;
trace_hvf_psci_call(param[0], param[1], param[2], param[3],
- arm_cpu->mp_affinity);
+ arm_cpu_mp_affinity(arm_cpu));
switch (param[0]) {
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c
index 9080a91d9c6..50d4b23d26b 100644
--- a/target/arm/tcg/psci.c
+++ b/target/arm/tcg/psci.c
@@ -215,7 +215,7 @@ err:
return;
cpu_off:
- ret = arm_set_cpu_off(cpu->mp_affinity);
+ ret = arm_set_cpu_off(arm_cpu_mp_affinity(cpu));
/* notreached */
/* sanity check in case something failed */
assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 19/36] target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2024-01-26 14:33 ` [PULL 18/36] target/arm: Create arm_cpu_mp_affinity Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 20/36] target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Peter Maydell
` (17 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Declare arm_cpu_mp_affinity() prototype in the new
"target/arm/multiprocessing.h" header so units in
hw/arm/ can use it without having to include the huge
target-specific "cpu.h".
File list to include the new header generated using:
$ git grep -lw arm_cpu_mp_affinity
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 6 +-----
target/arm/multiprocessing.h | 16 ++++++++++++++++
hw/arm/virt-acpi-build.c | 1 +
hw/arm/virt.c | 1 +
hw/arm/xlnx-versal-virt.c | 1 +
hw/misc/xlnx-versal-crl.c | 1 +
target/arm/arm-powerctl.c | 1 +
target/arm/cpu.c | 5 +++++
target/arm/hvf/hvf.c | 1 +
target/arm/tcg/psci.c | 1 +
10 files changed, 29 insertions(+), 5 deletions(-)
create mode 100644 target/arm/multiprocessing.h
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d1584bdb3b5..cecac4c0a12 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -26,6 +26,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#include "target/arm/multiprocessing.h"
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
@@ -1173,11 +1174,6 @@ void arm_cpu_post_init(Object *obj);
uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
-static inline uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
-{
- return cpu->mp_affinity;
-}
-
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_arm_cpu;
diff --git a/target/arm/multiprocessing.h b/target/arm/multiprocessing.h
new file mode 100644
index 00000000000..81715d345c2
--- /dev/null
+++ b/target/arm/multiprocessing.h
@@ -0,0 +1,16 @@
+/*
+ * ARM multiprocessor CPU helpers
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef TARGET_ARM_MULTIPROCESSING_H
+#define TARGET_ARM_MULTIPROCESSING_H
+
+#include "target/arm/cpu-qom.h"
+
+uint64_t arm_cpu_mp_affinity(ARMCPU *cpu);
+
+#endif
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 2127778c1ea..43ccc60f43c 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -59,6 +59,7 @@
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
#include "hw/virtio/virtio-acpi.h"
+#include "target/arm/multiprocessing.h"
#define ARM_SPI_BASE 32
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b3592798ea9..1e0df6ea3ad 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -74,6 +74,7 @@
#include "hw/arm/smmuv3.h"
#include "hw/acpi/acpi.h"
#include "target/arm/internals.h"
+#include "target/arm/multiprocessing.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/acpi/generic_event_device.h"
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 841ef69df66..29f4d2c2dce 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -20,6 +20,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
+#include "target/arm/multiprocessing.h"
#include "qom/object.h"
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
index 9bfa9baa157..1f1762ef163 100644
--- a/hw/misc/xlnx-versal-crl.c
+++ b/hw/misc/xlnx-versal-crl.c
@@ -19,6 +19,7 @@
#include "hw/resettable.h"
#include "target/arm/arm-powerctl.h"
+#include "target/arm/multiprocessing.h"
#include "hw/misc/xlnx-versal-crl.h"
#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index 6c86e901028..2b2055c6acc 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -16,6 +16,7 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "sysemu/tcg.h"
+#include "target/arm/multiprocessing.h"
#ifndef DEBUG_ARM_POWERCTL
#define DEBUG_ARM_POWERCTL 0
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5b5af7d4e1e..04296f2928f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1314,6 +1314,11 @@ uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
}
+uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
+{
+ return cpu->mp_affinity;
+}
+
static void arm_cpu_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 659401e12c7..71a26db1886 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -28,6 +28,7 @@
#include "arm-powerctl.h"
#include "target/arm/cpu.h"
#include "target/arm/internals.h"
+#include "target/arm/multiprocessing.h"
#include "trace/trace-target_arm_hvf.h"
#include "migration/vmstate.h"
diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c
index 50d4b23d26b..51d2ca3d30d 100644
--- a/target/arm/tcg/psci.c
+++ b/target/arm/tcg/psci.c
@@ -24,6 +24,7 @@
#include "sysemu/runstate.h"
#include "internals.h"
#include "arm-powerctl.h"
+#include "target/arm/multiprocessing.h"
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 20/36] target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2024-01-26 14:33 ` [PULL 19/36] target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 21/36] hw/cpu/a9mpcore: Build it only once Peter Maydell
` (16 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Missed in commit 2d56be5a29 ("target: Declare
FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'"). See
it for more details.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-qom.h | 3 +++
target/arm/cpu.h | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 02b914c8767..f795994135f 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -33,4 +33,7 @@ typedef struct AArch64CPUClass AArch64CPUClass;
DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
TYPE_AARCH64_CPU)
+#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
+#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
+
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cecac4c0a12..41659d0ef15 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2837,8 +2837,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
-#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 21/36] hw/cpu/a9mpcore: Build it only once
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2024-01-26 14:33 ` [PULL 20/36] target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 22/36] hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h' Peter Maydell
` (15 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/cpu/a9mpcore.c doesn't require "cpu.h" anymore.
By removing it, the unit become target agnostic:
we can build it once. Update meson.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-13-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/a9mpcore.c | 2 +-
hw/cpu/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index d03f57e579b..c30ef72c669 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -15,7 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
-#include "cpu.h"
+#include "target/arm/cpu-qom.h"
#define A9_GIC_NUM_PRIORITY_BITS 5
diff --git a/hw/cpu/meson.build b/hw/cpu/meson.build
index 6d319947ca0..38cdcfbe572 100644
--- a/hw/cpu/meson.build
+++ b/hw/cpu/meson.build
@@ -2,5 +2,5 @@ system_ss.add(files('core.c', 'cluster.c'))
system_ss.add(when: 'CONFIG_ARM11MPCORE', if_true: files('arm11mpcore.c'))
system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_mpcore.c'))
-specific_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c'))
+system_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c'))
specific_ss.add(when: 'CONFIG_A15MPCORE', if_true: files('a15mpcore.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 22/36] hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2024-01-26 14:33 ` [PULL 21/36] hw/cpu/a9mpcore: Build it only once Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 23/36] hw/misc/xlnx-versal-crl: Build it only once Peter Maydell
` (14 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
"target/arm/cpu.h" is target specific, any file including it
becomes target specific too, thus this is the same for any file
including "hw/misc/xlnx-versal-crl.h".
"hw/misc/xlnx-versal-crl.h" doesn't require any target specific
definition however, only the target-agnostic QOM definitions
from "target/arm/cpu-qom.h". Include the latter header to avoid
tainting unnecessary objects as target-specific.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-14-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/xlnx-versal-crl.h | 2 +-
hw/misc/xlnx-versal-crl.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h
index dfb8dff197d..dba6d3585d1 100644
--- a/include/hw/misc/xlnx-versal-crl.h
+++ b/include/hw/misc/xlnx-versal-crl.h
@@ -11,7 +11,7 @@
#include "hw/sysbus.h"
#include "hw/register.h"
-#include "target/arm/cpu.h"
+#include "target/arm/cpu-qom.h"
#define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
index 1f1762ef163..1a596f1cf57 100644
--- a/hw/misc/xlnx-versal-crl.c
+++ b/hw/misc/xlnx-versal-crl.c
@@ -18,6 +18,7 @@
#include "hw/register.h"
#include "hw/resettable.h"
+#include "target/arm/cpu.h"
#include "target/arm/arm-powerctl.h"
#include "target/arm/multiprocessing.h"
#include "hw/misc/xlnx-versal-crl.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 23/36] hw/misc/xlnx-versal-crl: Build it only once
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2024-01-26 14:33 ` [PULL 22/36] hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h' Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 24/36] target/arm: Expose M-profile register bank index definitions Peter Maydell
` (13 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/misc/xlnx-versal-crl.c doesn't require "cpu.h"
anymore. By removing it, the unit become target
agnostic: we can build it once. Update meson.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-15-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/xlnx-versal-crl.c | 1 -
hw/misc/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
index 1a596f1cf57..1f1762ef163 100644
--- a/hw/misc/xlnx-versal-crl.c
+++ b/hw/misc/xlnx-versal-crl.c
@@ -18,7 +18,6 @@
#include "hw/register.h"
#include "hw/resettable.h"
-#include "target/arm/cpu.h"
#include "target/arm/arm-powerctl.h"
#include "target/arm/multiprocessing.h"
#include "hw/misc/xlnx-versal-crl.h"
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 2ca2ce4b62e..e4ef1da5a53 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -96,8 +96,8 @@ system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
-specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
+ 'xlnx-versal-crl.c',
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
'xlnx-versal-cfu.c',
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 24/36] target/arm: Expose M-profile register bank index definitions
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2024-01-26 14:33 ` [PULL 23/36] hw/misc/xlnx-versal-crl: Build it only once Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 25/36] hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header Peter Maydell
` (12 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The ARMv7M QDev container accesses the QDev SysTickState
by its secure/non-secure bank index. In order to make
the "hw/intc/armv7m_nvic.h" header target-agnostic in
the next commit, first move the M-profile bank index
definitions to "target/arm/cpu-qom.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-16-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-qom.h | 15 +++++++++++++++
target/arm/cpu.h | 15 ---------------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index f795994135f..77bbc1f13c9 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -36,4 +36,19 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
+/* For M profile, some registers are banked secure vs non-secure;
+ * these are represented as a 2-element array where the first element
+ * is the non-secure copy and the second is the secure copy.
+ * When the CPU does not have implement the security extension then
+ * only the first element is used.
+ * This means that the copy for the current security state can be
+ * accessed via env->registerfield[env->v7m.secure] (whether the security
+ * extension is implemented or not).
+ */
+enum {
+ M_REG_NS = 0,
+ M_REG_S = 1,
+ M_REG_NUM_BANKS = 2,
+};
+
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 41659d0ef15..d6a79482adb 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -73,21 +73,6 @@
#define ARMV7M_EXCP_PENDSV 14
#define ARMV7M_EXCP_SYSTICK 15
-/* For M profile, some registers are banked secure vs non-secure;
- * these are represented as a 2-element array where the first element
- * is the non-secure copy and the second is the secure copy.
- * When the CPU does not have implement the security extension then
- * only the first element is used.
- * This means that the copy for the current security state can be
- * accessed via env->registerfield[env->v7m.secure] (whether the security
- * extension is implemented or not).
- */
-enum {
- M_REG_NS = 0,
- M_REG_S = 1,
- M_REG_NUM_BANKS = 2,
-};
-
/* ARM-specific interrupt pending bits. */
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 25/36] hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2024-01-26 14:33 ` [PULL 24/36] target/arm: Expose M-profile register bank index definitions Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 26/36] target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header Peter Maydell
` (11 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Now than we can access the M-profile bank index
definitions from the target-agnostic "cpu-qom.h"
header, we don't need the huge "cpu.h" anymore
(except in hw/arm/armv7m.c). Reduce its inclusion
to the source unit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-17-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/intc/armv7m_nvic.h | 2 +-
hw/arm/armv7m.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 6b4ae566c9a..89fe8aedaa9 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -10,7 +10,7 @@
#ifndef HW_ARM_ARMV7M_NVIC_H
#define HW_ARM_ARMV7M_NVIC_H
-#include "target/arm/cpu.h"
+#include "target/arm/cpu-qom.h"
#include "hw/sysbus.h"
#include "hw/timer/armv7m_systick.h"
#include "qom/object.h"
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 1f218277734..edcd8adc748 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -21,6 +21,7 @@
#include "qemu/module.h"
#include "qemu/log.h"
#include "target/arm/idau.h"
+#include "target/arm/cpu.h"
#include "target/arm/cpu-features.h"
#include "migration/vmstate.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 26/36] target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2024-01-26 14:33 ` [PULL 25/36] hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 27/36] target/arm: Move e2h_access() helper around Peter Maydell
` (10 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO
IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init()
handler. To allow non-ARM code to raise interrupt on ARM cores,
move they to 'target/arm/cpu-qom.h' which is non-ARM specific and
can be included by any hw/ file.
File list to include the new header generated using:
$ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)'
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-18-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-qom.h | 6 ++++++
target/arm/cpu.h | 6 ------
hw/arm/allwinner-a10.c | 1 +
hw/arm/allwinner-h3.c | 1 +
hw/arm/allwinner-r40.c | 1 +
hw/arm/armv7m.c | 1 +
hw/arm/aspeed_ast2400.c | 1 +
hw/arm/aspeed_ast2600.c | 1 +
hw/arm/bcm2836.c | 1 +
hw/arm/exynos4210.c | 1 +
hw/arm/fsl-imx25.c | 1 +
hw/arm/fsl-imx31.c | 1 +
hw/arm/fsl-imx6.c | 1 +
hw/arm/fsl-imx6ul.c | 1 +
hw/arm/fsl-imx7.c | 1 +
hw/arm/highbank.c | 1 +
hw/arm/integratorcp.c | 1 +
hw/arm/musicpal.c | 1 +
hw/arm/npcm7xx.c | 1 +
hw/arm/omap1.c | 1 +
hw/arm/omap2.c | 1 +
hw/arm/realview.c | 1 +
hw/arm/sbsa-ref.c | 1 +
hw/arm/strongarm.c | 1 +
hw/arm/versatilepb.c | 1 +
hw/arm/vexpress.c | 1 +
hw/arm/virt.c | 1 +
hw/arm/xilinx_zynq.c | 1 +
hw/arm/xlnx-versal.c | 1 +
hw/arm/xlnx-zynqmp.c | 1 +
target/arm/cpu.c | 1 +
31 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 77bbc1f13c9..8e032691dbf 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -36,6 +36,12 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
+/* Meanings of the ARMCPU object's four inbound GPIO lines */
+#define ARM_CPU_IRQ 0
+#define ARM_CPU_FIQ 1
+#define ARM_CPU_VIRQ 2
+#define ARM_CPU_VFIQ 3
+
/* For M profile, some registers are banked secure vs non-secure;
* these are represented as a 2-element array where the first element
* is the non-secure copy and the second is the secure copy.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d6a79482adb..e8df41d642e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -93,12 +93,6 @@
#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
#endif
-/* Meanings of the ARMCPU object's four inbound GPIO lines */
-#define ARM_CPU_IRQ 0
-#define ARM_CPU_FIQ 1
-#define ARM_CPU_VIRQ 2
-#define ARM_CPU_VFIQ 3
-
/* ARM-specific extra insn start words:
* 1: Conditional execution bits
* 2: Partial exception syndrome for data aborts
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 0135632996c..581dd45edf0 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -26,6 +26,7 @@
#include "hw/boards.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/loader.h"
+#include "target/arm/cpu-qom.h"
#define AW_A10_SRAM_A_BASE 0x00000000
#define AW_A10_DRAMC_BASE 0x01c01000
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index f05afddf7e0..2d684b5287b 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -30,6 +30,7 @@
#include "hw/loader.h"
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
+#include "target/arm/cpu-qom.h"
/* Memory map */
const hwaddr allwinner_h3_memmap[] = {
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
index a28e5b3886a..79976b0b54d 100644
--- a/hw/arm/allwinner-r40.c
+++ b/hw/arm/allwinner-r40.c
@@ -33,6 +33,7 @@
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-r40.h"
#include "hw/misc/allwinner-r40-dramc.h"
+#include "target/arm/cpu-qom.h"
/* Memory map */
const hwaddr allwinner_r40_memmap[] = {
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index edcd8adc748..7c68525a9e6 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -23,6 +23,7 @@
#include "target/arm/idau.h"
#include "target/arm/cpu.h"
#include "target/arm/cpu-features.h"
+#include "target/arm/cpu-qom.h"
#include "migration/vmstate.h"
/* Bitbanded IO. Each word corresponds to a single bit. */
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index 0baa2ff96e4..ad76035528f 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -21,6 +21,7 @@
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
+#include "target/arm/cpu-qom.h"
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 3a9a303ab8b..386a88d4e0f 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -16,6 +16,7 @@
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
+#include "target/arm/cpu-qom.h"
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
#define ASPEED_SOC_DPMCU_SIZE 0x00040000
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index b0674a22a6c..58a78780d2b 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -15,6 +15,7 @@
#include "hw/arm/bcm2836.h"
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
+#include "target/arm/cpu-qom.h"
struct BCM283XClass {
/*< private >*/
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index af511a153dd..6c428d8eeb4 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -36,6 +36,7 @@
#include "hw/arm/exynos4210.h"
#include "hw/sd/sdhci.h"
#include "hw/usb/hcd-ehci.h"
+#include "target/arm/cpu-qom.h"
#define EXYNOS4210_CHIPID_ADDR 0x10000000
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index 9d2fb75a689..4a49507ef19 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -28,6 +28,7 @@
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "chardev/char.h"
+#include "target/arm/cpu-qom.h"
#define IMX25_ESDHC_CAPABILITIES 0x07e20000
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index c0584e4dfcd..4b8d9b8e4fe 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -26,6 +26,7 @@
#include "exec/address-spaces.h"
#include "hw/qdev-properties.h"
#include "chardev/char.h"
+#include "target/arm/cpu-qom.h"
static void fsl_imx31_init(Object *obj)
{
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index af2e982b052..42f90588251 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -29,6 +29,7 @@
#include "chardev/char.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
+#include "target/arm/cpu-qom.h"
#define IMX6_ESDHC_CAPABILITIES 0x057834b4
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index e37b69a5e16..486a009deb8 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -25,6 +25,7 @@
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
+#include "target/arm/cpu-qom.h"
#define NAME_SIZE 20
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 474cfdc87c6..57281094918 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -26,6 +26,7 @@
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
+#include "target/arm/cpu-qom.h"
#define NAME_SIZE 20
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index c21e18d08fd..e6e27d69af5 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -36,6 +36,7 @@
#include "qemu/log.h"
#include "qom/object.h"
#include "cpu.h"
+#include "target/arm/cpu-qom.h"
#define SMP_BOOT_ADDR 0x100
#define SMP_BOOT_REG 0x40
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 1830e1d7850..5600616a4dd 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -28,6 +28,7 @@
#include "hw/sd/sd.h"
#include "qom/object.h"
#include "audio/audio.h"
+#include "target/arm/cpu-qom.h"
#define TYPE_INTEGRATOR_CM "integrator_core"
OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 6987472871e..a2d25139e20 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -39,6 +39,7 @@
#include "hw/net/mv88w8618_eth.h"
#include "audio/audio.h"
#include "qemu/error-report.h"
+#include "target/arm/cpu-qom.h"
#define MP_MISC_BASE 0x80002000
#define MP_MISC_SIZE 0x00001000
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 7fb0a233b2d..e3243a520d8 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "sysemu/sysemu.h"
+#include "target/arm/cpu-qom.h"
/*
* This covers the whole MMIO space. We'll use this to catch any MMIO accesses
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index d5438156ee9..86ee336e599 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -40,6 +40,7 @@
#include "hw/sysbus.h"
#include "qemu/cutils.h"
#include "qemu/bcd.h"
+#include "target/arm/cpu-qom.h"
static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz)
{
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index f170728e7ec..f159fb73ea9 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -39,6 +39,7 @@
#include "hw/sysbus.h"
#include "hw/boards.h"
#include "audio/audio.h"
+#include "target/arm/cpu-qom.h"
/* Enhanced Audio Controller (CODEC only) */
struct omap_eac_s {
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 132217b2edd..566deff9ced 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -30,6 +30,7 @@
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/sd/sd.h"
#include "audio/audio.h"
+#include "target/arm/cpu-qom.h"
#define SMP_BOOT_ADDR 0xe0000000
#define SMP_BOOTREG_ADDR 0x10000030
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index b8857d1e9e4..d6081bfc41f 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -50,6 +50,7 @@
#include "net/net.h"
#include "qapi/qmp/qlist.h"
#include "qom/object.h"
+#include "target/arm/cpu-qom.h"
#define RAMLIMIT_GB 8192
#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index fef3638acaa..75637869cba 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -46,6 +46,7 @@
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qom/object.h"
+#include "target/arm/cpu-qom.h"
//#define DEBUG
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 4b2257787b2..15b5ed0cedc 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -27,6 +27,7 @@
#include "hw/sd/sd.h"
#include "qom/object.h"
#include "audio/audio.h"
+#include "target/arm/cpu-qom.h"
#define VERSATILE_FLASH_ADDR 0x34000000
#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index fd981f4c33e..49dbcdcbf0c 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -46,6 +46,7 @@
#include "qapi/qmp/qlist.h"
#include "qom/object.h"
#include "audio/audio.h"
+#include "target/arm/cpu-qom.h"
#define VEXPRESS_BOARD_ID 0x8e0
#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 1e0df6ea3ad..64802446cb1 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -73,6 +73,7 @@
#include "standard-headers/linux/input.h"
#include "hw/arm/smmuv3.h"
#include "hw/acpi/acpi.h"
+#include "target/arm/cpu-qom.h"
#include "target/arm/internals.h"
#include "target/arm/multiprocessing.h"
#include "hw/mem/pc-dimm.h"
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index d4c817ecdc0..5809fc32af9 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -38,6 +38,7 @@
#include "sysemu/reset.h"
#include "qom/object.h"
#include "exec/tswap.h"
+#include "target/arm/cpu-qom.h"
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 9600551c442..87fdb39d430 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -23,6 +23,7 @@
#include "hw/misc/unimp.h"
#include "hw/arm/xlnx-versal.h"
#include "qemu/log.h"
+#include "target/arm/cpu-qom.h"
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 5905a330151..38cb34942f8 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -25,6 +25,7 @@
#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "kvm_arm.h"
+#include "target/arm/cpu-qom.h"
#define GIC_NUM_SPI_INTR 160
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 04296f2928f..4807a4fea0d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -48,6 +48,7 @@
#include "disas/capstone.h"
#include "fpu/softfloat.h"
#include "cpregs.h"
+#include "target/arm/cpu-qom.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 27/36] target/arm: Move e2h_access() helper around
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2024-01-26 14:33 ` [PULL 26/36] target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 28/36] target/arm: Move GTimer definitions to new 'gtimer.h' header Peter Maydell
` (9 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
e2h_access() was added in commit bb5972e439 ("target/arm:
Add VHE timer register redirection and aliasing") close to
the generic_timer_cp_reginfo[] array, but isn't used until
vhe_reginfo[] definition. Move it closer to the other e2h
helpers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-19-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 29 +++++++++++++++--------------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e068d353831..e07b2af8a3d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3345,20 +3345,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
},
};
-static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
- bool isread)
-{
- if (arm_current_el(env) == 1) {
- /* This must be a FEAT_NV access */
- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
- return CP_ACCESS_OK;
- }
- if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_TRAP;
- }
- return CP_ACCESS_OK;
-}
-
#else
/*
@@ -6546,6 +6532,21 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
};
#ifndef CONFIG_USER_ONLY
+
+static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 1) {
+ /* This must be a FEAT_NV access */
+ /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
+ return CP_ACCESS_OK;
+ }
+ if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
+ return CP_ACCESS_TRAP;
+ }
+ return CP_ACCESS_OK;
+}
+
/* Test if system register redirection is to occur in the current state. */
static bool redirect_for_e2h(CPUARMState *env)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 28/36] target/arm: Move GTimer definitions to new 'gtimer.h' header
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2024-01-26 14:33 ` [PULL 27/36] target/arm: Move e2h_access() helper around Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 29/36] hw/arm: Build various units only once Peter Maydell
` (8 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move Arm A-class Generic Timer definitions to the new
"target/arm/gtimer.h" header so units in hw/ which don't
need access to ARMCPU internals can use them without
having to include the huge "cpu.h".
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-20-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 8 +-------
target/arm/gtimer.h | 21 +++++++++++++++++++++
hw/arm/allwinner-h3.c | 1 +
hw/arm/allwinner-r40.c | 1 +
hw/arm/bcm2836.c | 1 +
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt.c | 1 +
hw/arm/xlnx-versal.c | 1 +
hw/arm/xlnx-zynqmp.c | 1 +
hw/cpu/a15mpcore.c | 1 +
target/arm/cpu.c | 1 +
target/arm/helper.c | 1 +
target/arm/hvf/hvf.c | 1 +
target/arm/kvm.c | 1 +
target/arm/machine.c | 1 +
15 files changed, 35 insertions(+), 7 deletions(-)
create mode 100644 target/arm/gtimer.h
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e8df41d642e..d3477b16018 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -27,6 +27,7 @@
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
+#include "target/arm/gtimer.h"
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
@@ -140,13 +141,6 @@ typedef struct ARMGenericTimer {
uint64_t ctl; /* Timer Control register */
} ARMGenericTimer;
-#define GTIMER_PHYS 0
-#define GTIMER_VIRT 1
-#define GTIMER_HYP 2
-#define GTIMER_SEC 3
-#define GTIMER_HYPVIRT 4
-#define NUM_GTIMERS 5
-
#define VTCR_NSW (1u << 29)
#define VTCR_NSA (1u << 30)
#define VSTCR_SW VTCR_NSW
diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
new file mode 100644
index 00000000000..b992941bef1
--- /dev/null
+++ b/target/arm/gtimer.h
@@ -0,0 +1,21 @@
+/*
+ * ARM generic timer definitions for Arm A-class CPU
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef TARGET_ARM_GTIMER_H
+#define TARGET_ARM_GTIMER_H
+
+enum {
+ GTIMER_PHYS = 0,
+ GTIMER_VIRT = 1,
+ GTIMER_HYP = 2,
+ GTIMER_SEC = 3,
+ GTIMER_HYPVIRT = 4,
+#define NUM_GTIMERS 5
+};
+
+#endif
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 2d684b5287b..380e0ec11d6 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -31,6 +31,7 @@
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
/* Memory map */
const hwaddr allwinner_h3_memmap[] = {
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
index 79976b0b54d..eef1fc196e5 100644
--- a/hw/arm/allwinner-r40.c
+++ b/hw/arm/allwinner-r40.c
@@ -34,6 +34,7 @@
#include "hw/arm/allwinner-r40.h"
#include "hw/misc/allwinner-r40-dramc.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
/* Memory map */
const hwaddr allwinner_r40_memmap[] = {
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 58a78780d2b..e3ba18a8ec1 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -16,6 +16,7 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
struct BCM283XClass {
/*< private >*/
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index d6081bfc41f..85cb68d5463 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -51,6 +51,7 @@
#include "qapi/qmp/qlist.h"
#include "qom/object.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
#define RAMLIMIT_GB 8192
#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 64802446cb1..e6ead2c5c89 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -76,6 +76,7 @@
#include "target/arm/cpu-qom.h"
#include "target/arm/internals.h"
#include "target/arm/multiprocessing.h"
+#include "target/arm/gtimer.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/acpi/generic_event_device.h"
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 87fdb39d430..2798df3730d 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -24,6 +24,7 @@
#include "hw/arm/xlnx-versal.h"
#include "qemu/log.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 38cb34942f8..65901c6e74b 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -26,6 +26,7 @@
#include "sysemu/sysemu.h"
#include "kvm_arm.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
#define GIC_NUM_SPI_INTR 160
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index bfd8aa56448..967d8d3dd50 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -26,6 +26,7 @@
#include "hw/qdev-properties.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
+#include "target/arm/gtimer.h"
static void a15mp_priv_set_irq(void *opaque, int irq, int level)
{
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4807a4fea0d..b60e1030469 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -49,6 +49,7 @@
#include "fpu/softfloat.h"
#include "cpregs.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e07b2af8a3d..945d8571a61 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -30,6 +30,7 @@
#include "semihosting/common-semi.h"
#endif
#include "cpregs.h"
+#include "target/arm/gtimer.h"
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 71a26db1886..e5f0f60093e 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -29,6 +29,7 @@
#include "target/arm/cpu.h"
#include "target/arm/internals.h"
#include "target/arm/multiprocessing.h"
+#include "target/arm/gtimer.h"
#include "trace/trace-target_arm_hvf.h"
#include "migration/vmstate.h"
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 8f52b211f9a..81813030a5a 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -38,6 +38,7 @@
#include "qemu/log.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ghes.h"
+#include "target/arm/gtimer.h"
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 542be14bec2..9d7dbaea54c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -7,6 +7,7 @@
#include "internals.h"
#include "cpu-features.h"
#include "migration/cpu.h"
+#include "target/arm/gtimer.h"
static bool vfp_needed(void *opaque)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 29/36] hw/arm: Build various units only once
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2024-01-26 14:33 ` [PULL 28/36] target/arm: Move GTimer definitions to new 'gtimer.h' header Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 30/36] fsl-imx6ul: Add various missing unimplemented devices Peter Maydell
` (7 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Various files in hw/arm/ don't require "cpu.h" anymore.
Except virt-acpi-build.c, all of them don't require any
ARM specific knowledge anymore and can be build once as
target agnostic units. Update meson accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-21-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/collie.c | 1 -
hw/arm/gumstix.c | 1 -
hw/arm/integratorcp.c | 1 -
hw/arm/mainstone.c | 1 -
hw/arm/musicpal.c | 1 -
hw/arm/omap2.c | 1 -
hw/arm/omap_sx1.c | 1 -
hw/arm/palm.c | 1 -
hw/arm/spitz.c | 1 -
hw/arm/strongarm.c | 1 -
hw/arm/versatilepb.c | 1 -
hw/arm/vexpress.c | 1 -
hw/arm/virt-acpi-build.c | 1 -
hw/arm/xilinx_zynq.c | 1 -
hw/arm/xlnx-versal-virt.c | 1 -
hw/arm/z2.c | 1 -
hw/arm/meson.build | 23 ++++++++++++-----------
17 files changed, 12 insertions(+), 27 deletions(-)
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index a0ad1b8dc7e..eaa5c52d45a 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -17,7 +17,6 @@
#include "hw/arm/boot.h"
#include "hw/block/flash.h"
#include "exec/address-spaces.h"
-#include "cpu.h"
#include "qom/object.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index 2ca4140c9fc..3f2bcaa24e4 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -44,7 +44,6 @@
#include "hw/boards.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
-#include "cpu.h"
#define CONNEX_FLASH_SIZE (16 * MiB)
#define CONNEX_RAM_SIZE (64 * MiB)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 5600616a4dd..793262eca8c 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/boards.h"
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index 68329c46178..fc14e050608 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -23,7 +23,6 @@
#include "hw/block/flash.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
-#include "cpu.h"
/* Device addresses */
#define MST_FPGA_PHYS 0x08000000
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index a2d25139e20..0fe0160b48b 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -12,7 +12,6 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
-#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index f159fb73ea9..d9683276c68 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -21,7 +21,6 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
-#include "cpu.h"
#include "exec/address-spaces.h"
#include "sysemu/blockdev.h"
#include "sysemu/qtest.h"
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 4bf1579f8c1..62d7915fb8f 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -35,7 +35,6 @@
#include "hw/block/flash.h"
#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
-#include "cpu.h"
#include "qemu/cutils.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index b86f2c331bb..8c4c8316140 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -29,7 +29,6 @@
#include "hw/input/tsc2xxx.h"
#include "hw/irq.h"
#include "hw/loader.h"
-#include "cpu.h"
#include "qemu/cutils.h"
#include "qom/object.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 1d680b61e24..643a02b1807 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -33,7 +33,6 @@
#include "hw/adc/max111x.h"
#include "migration/vmstate.h"
#include "exec/address-spaces.h"
-#include "cpu.h"
#include "qom/object.h"
#include "audio/audio.h"
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index 75637869cba..7fd99a0f144 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -28,7 +28,6 @@
*/
#include "qemu/osdep.h"
-#include "cpu.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 15b5ed0cedc..1d813aa23b5 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 49dbcdcbf0c..f1b45245d5d 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -24,7 +24,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
-#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 43ccc60f43c..17aeec7a6f5 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -32,7 +32,6 @@
#include "qemu/error-report.h"
#include "trace.h"
#include "hw/core/cpu.h"
-#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/nvram/fw_cfg_acpi.h"
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 5809fc32af9..66d0de139f2 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -18,7 +18,6 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
-#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "net/net.h"
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 29f4d2c2dce..94942c55dff 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -16,7 +16,6 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/arm/fdt.h"
-#include "cpu.h"
#include "hw/qdev-properties.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 83741a49092..a67fba2cfd2 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -25,7 +25,6 @@
#include "hw/audio/wm8750.h"
#include "audio/audio.h"
#include "exec/address-spaces.h"
-#include "cpu.h"
#include "qom/object.h"
#include "qapi/error.h"
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index bb92b27db3e..c4017790670 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -9,23 +9,14 @@ arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
-arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
-arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
-arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
-arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
-arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
-arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
-arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
-arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
-arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
@@ -33,8 +24,7 @@ arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c'))
arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c'))
arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c'))
arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c'))
-arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c'))
-arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
+arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c'))
arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
@@ -69,8 +59,19 @@ arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
arm_ss.add(when: 'CONFIG_XEN', if_true: files('xen_arm.c'))
system_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
+system_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
+system_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
+system_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
+system_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
+system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap2.c'))
system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
+system_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
+system_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
+system_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
system_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
+system_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
+system_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
+system_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
hw_arch += {'arm': arm_ss}
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 30/36] fsl-imx6ul: Add various missing unimplemented devices
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (28 preceding siblings ...)
2024-01-26 14:33 ` [PULL 29/36] hw/arm: Build various units only once Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 31/36] docs/system/arm/virt.rst: Add note on CPU features off by default Peter Maydell
` (6 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Guenter Roeck <linux@roeck-us.net>
Add MMDC, OCOTP, SQPI, CAAM, and USBMISC as unimplemented devices.
This allows operating systems such as Linux to run emulations such as
mcimx6ul-evk.
Before commit 0cd4926b85 ("Refactor i.MX6UL processor code"), the affected
memory ranges were covered by the unimplemented DAP device. The commit
reduced the DAP address range from 0x100000 to 4kB, and the emulation
thus no longer covered the various unimplemented devices in the affected
address range.
Fixes: 0cd4926b85 ("Refactor i.MX6UL processor code")
Cc: Jean-Christophe Dubois <jcd@tribudubois.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240120005356.2599547-1-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/fsl-imx6ul.h | 2 ++
hw/arm/fsl-imx6ul.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 14390f60144..8277b0e8b2c 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -182,6 +182,8 @@ enum FslIMX6ULMemoryMap {
FSL_IMX6UL_ENET1_ADDR = 0x02188000,
FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
+ FSL_IMX6UL_USBO2_USBMISC_SIZE = 0x200,
+
FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000,
FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200,
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index 486a009deb8..343bd65d1b2 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -193,6 +193,36 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
FSL_IMX6UL_A7MPCORE_DAP_SIZE);
+ /*
+ * MMDC
+ */
+ create_unimplemented_device("a7mpcore-mmdc", FSL_IMX6UL_MMDC_CFG_ADDR,
+ FSL_IMX6UL_MMDC_CFG_SIZE);
+
+ /*
+ * OCOTP
+ */
+ create_unimplemented_device("a7mpcore-ocotp", FSL_IMX6UL_OCOTP_CTRL_ADDR,
+ FSL_IMX6UL_OCOTP_CTRL_SIZE);
+
+ /*
+ * QSPI
+ */
+ create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_QSPI_ADDR,
+ FSL_IMX6UL_QSPI_SIZE);
+
+ /*
+ * CAAM
+ */
+ create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_CAAM_ADDR,
+ FSL_IMX6UL_CAAM_SIZE);
+
+ /*
+ * USBMISC
+ */
+ create_unimplemented_device("a7mpcore-usbmisc", FSL_IMX6UL_USBO2_USBMISC_ADDR,
+ FSL_IMX6UL_USBO2_USBMISC_SIZE);
+
/*
* GPTs
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 31/36] docs/system/arm/virt.rst: Add note on CPU features off by default
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (29 preceding siblings ...)
2024-01-26 14:33 ` [PULL 30/36] fsl-imx6ul: Add various missing unimplemented devices Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 32/36] hw/char/imx_serial: Implement receive FIFO and ageing timer Peter Maydell
` (5 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Gustavo Romero <gustavo.romero@linaro.org>
Add a note on CPU features that are off by default in `virt` machines.
Some CPU features will remain off even if a CPU-capable CPU (e.g.,
`-cpu max`) is selected because they require support in both the CPU
itself and in the wider system. Therefore, the user, besides selecting a
CPU that supports such features, must also turn on the feature using a
machine option.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240122211215.95073-1-gustavo.romero@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/virt.rst | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index c245c52b7ac..26fcba00b76 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -69,6 +69,19 @@ Supported guest CPU types:
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
specify a CPU type.
+Also, please note that passing ``max`` CPU (i.e. ``-cpu max``) won't
+enable all the CPU features for a given ``virt`` machine. Where a CPU
+architectural feature requires support in both the CPU itself and in the
+wider system (e.g. the MTE feature), it may not be enabled by default,
+but instead requires a machine option to enable it.
+
+For example, MTE support must be enabled with ``-machine virt,mte=on``,
+as well as by selecting an MTE-capable CPU (e.g., ``max``) with the
+``-cpu`` option.
+
+See the machine-specific options below, or check them for a given machine
+by passing the ``help`` suboption, like: ``-machine virt-9.0,help``.
+
Graphics output is available, but unlike the x86 PC machine types
there is no default display device enabled: you should select one from
the Display devices section of "-device help". The recommended option
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 32/36] hw/char/imx_serial: Implement receive FIFO and ageing timer
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (30 preceding siblings ...)
2024-01-26 14:33 ` [PULL 31/36] docs/system/arm/virt.rst: Add note on CPU features off by default Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 33/36] target/arm: Fix A64 scalar SQSHRN and SQRSHRN Peter Maydell
` (4 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Rayhan Faizel <rayhan.faizel@gmail.com>
This patch implements a 32 half word FIFO as per imx serial device
specifications. If a non empty FIFO is below the trigger level, an
ageing timer will tick for a duration of 8 characters. On expiry,
AGTIM will be set triggering an interrupt. AGTIM timer resets when
there is activity in the receive FIFO.
Otherwise, RRDY is set when trigger level is exceeded. The receive
trigger level is 8 in newer kernel versions and 1 in older ones.
This change will break migration compatibility for the imx boards.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Message-id: 20240125151931.83494-1-rayhan.faizel@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: commit message tidyups]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/char/imx_serial.h | 20 ++++++-
hw/char/imx_serial.c | 102 ++++++++++++++++++++++++++++++-----
2 files changed, 108 insertions(+), 14 deletions(-)
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index b823f945195..65f0e97c76b 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -21,12 +21,16 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
+#include "qemu/fifo32.h"
#define TYPE_IMX_SERIAL "imx.serial"
OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
+#define FIFO_SIZE 32
+
#define URXD_CHARRDY (1<<15) /* character read is valid */
#define URXD_ERR (1<<14) /* Character has error */
+#define URXD_OVRRUN (1<<13) /* 32nd character in RX FIFO */
#define URXD_FRMERR (1<<12) /* Character has frame error */
#define URXD_BRK (1<<11) /* Break received */
@@ -65,11 +69,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
#define UCR1_UARTEN (1<<0) /* UART Enable */
+#define UCR2_ATEN (1<<3) /* Ageing Timer Enable */
#define UCR2_TXEN (1<<2) /* Transmitter enable */
#define UCR2_RXEN (1<<1) /* Receiver enable */
#define UCR2_SRST (1<<0) /* Reset complete */
#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
+#define UCR4_OREN BIT(1) /* Overrun interrupt enable */
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */
@@ -78,13 +84,25 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define UTS1_TXFULL (1<<4)
#define UTS1_RXFULL (1<<3)
+#define TL_MASK 0x3f
+
+ /* Bit time in nanoseconds assuming maximum baud rate of 115200 */
+#define BIT_TIME_NS 8681
+
+/* Assume 8 bits per character */
+#define NUM_BITS 8
+
+/* Ageing timer triggers after 8 characters */
+#define AGE_DURATION_NS (8 * NUM_BITS * BIT_TIME_NS)
+
struct IMXSerialState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
- int32_t readbuff;
+ QEMUTimer ageing_timer;
+ Fifo32 rx_fifo;
uint32_t usr1;
uint32_t usr2;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 1df862eb7ff..ba37be6faab 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -26,6 +26,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "qemu/fifo32.h"
#ifndef DEBUG_IMX_UART
#define DEBUG_IMX_UART 0
@@ -41,10 +42,11 @@
static const VMStateDescription vmstate_imx_serial = {
.name = TYPE_IMX_SERIAL,
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (const VMStateField[]) {
- VMSTATE_INT32(readbuff, IMXSerialState),
+ VMSTATE_FIFO32(rx_fifo, IMXSerialState),
+ VMSTATE_TIMER(ageing_timer, IMXSerialState),
VMSTATE_UINT32(usr1, IMXSerialState),
VMSTATE_UINT32(usr2, IMXSerialState),
VMSTATE_UINT32(ucr1, IMXSerialState),
@@ -71,6 +73,10 @@ static void imx_update(IMXSerialState *s)
* following:
*/
usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
+ /*
+ * Interrupt if AGTIM is set (ageing timer interrupt in RxFIFO)
+ */
+ usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0;
/*
* Bits that we want in USR2 are not as conveniently laid out,
* unfortunately.
@@ -78,15 +84,66 @@ static void imx_update(IMXSerialState *s)
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
/*
* TCEN and TXDC are both bit 3
+ * ORE and OREN are both bit 1
* RDR and DREN are both bit 0
*/
- mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN);
+ mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN | UCR4_OREN);
usr2 = s->usr2 & mask;
qemu_set_irq(s->irq, usr1 || usr2);
}
+static void imx_serial_rx_fifo_push(IMXSerialState *s, uint32_t value)
+{
+ uint32_t pushed_value = value;
+ if (fifo32_is_full(&s->rx_fifo)) {
+ /* Set ORE if FIFO is already full */
+ s->usr2 |= USR2_ORE;
+ } else {
+ if (fifo32_num_used(&s->rx_fifo) == FIFO_SIZE - 1) {
+ /* Set OVRRUN on 32nd character in FIFO */
+ pushed_value |= URXD_ERR | URXD_OVRRUN;
+ }
+ fifo32_push(&s->rx_fifo, pushed_value);
+ }
+}
+
+static uint32_t imx_serial_rx_fifo_pop(IMXSerialState *s)
+{
+ if (fifo32_is_empty(&s->rx_fifo)) {
+ return 0;
+ }
+ return fifo32_pop(&s->rx_fifo);
+}
+
+static void imx_serial_rx_fifo_ageing_timer_int(void *opaque)
+{
+ IMXSerialState *s = (IMXSerialState *) opaque;
+ s->usr1 |= USR1_AGTIM;
+ imx_update(s);
+}
+
+static void imx_serial_rx_fifo_ageing_timer_restart(void *opaque)
+{
+ /*
+ * Ageing timer starts ticking when
+ * RX FIFO is non empty and below trigger level.
+ * Timer is reset if new character is received or
+ * a FIFO read occurs.
+ * Timer triggers an interrupt when duration of
+ * 8 characters has passed (assuming 115200 baudrate).
+ */
+ IMXSerialState *s = (IMXSerialState *) opaque;
+
+ if (!(s->usr1 & USR1_RRDY) && !(s->uts1 & UTS1_RXEMPTY)) {
+ timer_mod_ns(&s->ageing_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + AGE_DURATION_NS);
+ } else {
+ timer_del(&s->ageing_timer);
+ }
+}
+
static void imx_serial_reset(IMXSerialState *s)
{
@@ -102,7 +159,9 @@ static void imx_serial_reset(IMXSerialState *s)
s->ucr3 = 0x700;
s->ubmr = 0;
s->ubrc = 4;
- s->readbuff = URXD_ERR;
+
+ fifo32_reset(&s->rx_fifo);
+ timer_del(&s->ageing_timer);
}
static void imx_serial_reset_at_boot(DeviceState *dev)
@@ -125,20 +184,28 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
- uint32_t c;
+ uint32_t c, rx_used;
+ uint8_t rxtl = s->ufcr & TL_MASK;
DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
switch (offset >> 2) {
case 0x0: /* URXD */
- c = s->readbuff;
+ c = imx_serial_rx_fifo_pop(s);
if (!(s->uts1 & UTS1_RXEMPTY)) {
/* Character is valid */
c |= URXD_CHARRDY;
- s->usr1 &= ~USR1_RRDY;
- s->usr2 &= ~USR2_RDR;
- s->uts1 |= UTS1_RXEMPTY;
+ rx_used = fifo32_num_used(&s->rx_fifo);
+ /* Clear RRDY if below threshold */
+ if (rx_used < rxtl) {
+ s->usr1 &= ~USR1_RRDY;
+ }
+ if (rx_used == 0) {
+ s->usr2 &= ~USR2_RDR;
+ s->uts1 |= UTS1_RXEMPTY;
+ }
imx_update(s);
+ imx_serial_rx_fifo_ageing_timer_restart(s);
qemu_chr_fe_accept_input(&s->chr);
}
return c;
@@ -300,19 +367,24 @@ static void imx_serial_write(void *opaque, hwaddr offset,
static int imx_can_receive(void *opaque)
{
IMXSerialState *s = (IMXSerialState *)opaque;
- return !(s->usr1 & USR1_RRDY);
+ return s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE;
}
static void imx_put_data(void *opaque, uint32_t value)
{
IMXSerialState *s = (IMXSerialState *)opaque;
+ uint8_t rxtl = s->ufcr & TL_MASK;
DPRINTF("received char\n");
+ imx_serial_rx_fifo_push(s, value);
+ if (fifo32_num_used(&s->rx_fifo) >= rxtl) {
+ s->usr1 |= USR1_RRDY;
+ }
+
+ imx_serial_rx_fifo_ageing_timer_restart(s);
- s->usr1 |= USR1_RRDY;
s->usr2 |= USR2_RDR;
s->uts1 &= ~UTS1_RXEMPTY;
- s->readbuff = value;
if (value & URXD_BRK) {
s->usr2 |= USR2_BRCD;
}
@@ -345,6 +417,10 @@ static void imx_serial_realize(DeviceState *dev, Error **errp)
{
IMXSerialState *s = IMX_SERIAL(dev);
+ fifo32_create(&s->rx_fifo, FIFO_SIZE);
+ timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL,
+ imx_serial_rx_fifo_ageing_timer_int, s);
+
DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 33/36] target/arm: Fix A64 scalar SQSHRN and SQRSHRN
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (31 preceding siblings ...)
2024-01-26 14:33 ` [PULL 32/36] hw/char/imx_serial: Implement receive FIFO and ageing timer Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 34/36] bswap.h: Fix const_le64() macro Peter Maydell
` (3 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
In commit 1b7bc9b5c8bf374dd we changed handle_vec_simd_sqshrn() so
that instead of starting with a 0 value and depositing in each new
element from the narrowing operation, it instead started with the raw
result of the narrowing operation of the first element.
This is fine in the vector case, because the deposit operations for
the second and subsequent elements will always overwrite any higher
bits that might have been in the first element's result value in
tcg_rd. However in the scalar case we only go through this loop
once. The effect is that for a signed narrowing operation, if the
result is negative then we will now return a value where the bits
above the first element are incorrectly 1 (because the narrowfn
returns a sign-extended result, not one that is truncated to the
element size).
Fix this by using an extract operation to get exactly the correct
bits of the output of the narrowfn for element 1, instead of a
plain move.
Cc: qemu-stable@nongnu.org
Fixes: 1b7bc9b5c8bf374dd3 ("target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2089
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240123153416.877308-1-peter.maydell@linaro.org
---
target/arm/tcg/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 27335e85407..340265beb05 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8343,7 +8343,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
narrowfn(tcg_rd_narrowed, tcg_env, tcg_rd);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
if (i == 0) {
- tcg_gen_mov_i64(tcg_final, tcg_rd);
+ tcg_gen_extract_i64(tcg_final, tcg_rd, 0, esize);
} else {
tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 34/36] bswap.h: Fix const_le64() macro
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (32 preceding siblings ...)
2024-01-26 14:33 ` [PULL 33/36] target/arm: Fix A64 scalar SQSHRN and SQRSHRN Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 35/36] target/arm: Fix incorrect aa64_tidcp1 feature check Peter Maydell
` (2 subsequent siblings)
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
The const_le64() macro introduced in commit 845d80a8c7b187 turns out
to have a bug which means that on big-endian systems the compiler
complains if the argument isn't already a 64-bit type. This hasn't
caused a problem yet, because there are no in-tree uses, but it
means it's not possible for anybody to add one without it failing CI.
This example is from an attempted use of it with the argument '0',
from the s390 CI runner's gcc:
../block/blklogwrites.c: In function ‘blk_log_writes_co_do_log’:
../include/qemu/bswap.h:148:36: error: left shift count >= width of
type [-Werror=shift-count-overflow]
148 | ((((_x) & 0x00000000000000ffU) << 56) | \
| ^~
../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’
409 | .nr_entries = const_le64(0),
| ^~~~~~~~~~
../include/qemu/bswap.h:149:36: error: left shift count >= width of
type [-Werror=shift-count-overflow]
149 | (((_x) & 0x000000000000ff00U) << 40) | \
| ^~
../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’
409 | .nr_entries = const_le64(0),
| ^~~~~~~~~~
cc1: all warnings being treated as errors
Fix this by making all the constants in the macro have the ULL
suffix. This will cause them all to be 64-bit integers, which means
the result of the logical & will also be an unsigned 64-bit type,
even if the input to the macro is a smaller type, and so the shifts
will be in range.
Fixes: 845d80a8c7b187 ("qemu/bswap: Add const_le64()")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Message-id: 20240122173735.472951-1-peter.maydell@linaro.org
---
include/qemu/bswap.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index 933a66ee87e..bd67468e5e4 100644
--- a/include/qemu/bswap.h
+++ b/include/qemu/bswap.h
@@ -145,14 +145,14 @@ CPU_CONVERT(le, 64, uint64_t)
*/
#if HOST_BIG_ENDIAN
# define const_le64(_x) \
- ((((_x) & 0x00000000000000ffU) << 56) | \
- (((_x) & 0x000000000000ff00U) << 40) | \
- (((_x) & 0x0000000000ff0000U) << 24) | \
- (((_x) & 0x00000000ff000000U) << 8) | \
- (((_x) & 0x000000ff00000000U) >> 8) | \
- (((_x) & 0x0000ff0000000000U) >> 24) | \
- (((_x) & 0x00ff000000000000U) >> 40) | \
- (((_x) & 0xff00000000000000U) >> 56))
+ ((((_x) & 0x00000000000000ffULL) << 56) | \
+ (((_x) & 0x000000000000ff00ULL) << 40) | \
+ (((_x) & 0x0000000000ff0000ULL) << 24) | \
+ (((_x) & 0x00000000ff000000ULL) << 8) | \
+ (((_x) & 0x000000ff00000000ULL) >> 8) | \
+ (((_x) & 0x0000ff0000000000ULL) >> 24) | \
+ (((_x) & 0x00ff000000000000ULL) >> 40) | \
+ (((_x) & 0xff00000000000000ULL) >> 56))
# define const_le32(_x) \
((((_x) & 0x000000ffU) << 24) | \
(((_x) & 0x0000ff00U) << 8) | \
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 35/36] target/arm: Fix incorrect aa64_tidcp1 feature check
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (33 preceding siblings ...)
2024-01-26 14:33 ` [PULL 34/36] bswap.h: Fix const_le64() macro Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-26 14:33 ` [PULL 36/36] hw/arm: add PCIe to Freescale i.MX6 Peter Maydell
2024-01-27 13:00 ` [PULL 00/36] target-arm queue Peter Maydell
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
A typo in the implementation of isar_feature_aa64_tidcp1() means we
were checking the field in the wrong ID register, so we might have
provided the feature on CPUs that don't have it and not provided
it on CPUs that should have it. Correct this bug.
Cc: qemu-stable@nongnu.org
Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1"
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240123160333.958841-1-peter.maydell@linaro.org
---
target/arm/cpu-features.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 028795ff23f..7567854db63 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -773,7 +773,7 @@ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0;
}
static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PULL 36/36] hw/arm: add PCIe to Freescale i.MX6
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (34 preceding siblings ...)
2024-01-26 14:33 ` [PULL 35/36] target/arm: Fix incorrect aa64_tidcp1 feature check Peter Maydell
@ 2024-01-26 14:33 ` Peter Maydell
2024-01-27 13:00 ` [PULL 00/36] target-arm queue Peter Maydell
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
From: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Message-id: 20240108140325.1291-1-n.ostrenkov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/fsl-imx6.h | 44 ++++++++++++++++++++-------------------
hw/arm/fsl-imx6.c | 25 ++++++++++++++++++++++
hw/arm/Kconfig | 2 ++
3 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 519b871014a..61c593ffd24 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -32,6 +32,7 @@
#include "hw/net/imx_fec.h"
#include "hw/usb/chipidea.h"
#include "hw/usb/imx-usb-phy.h"
+#include "hw/pci-host/designware.h"
#include "exec/memory.h"
#include "cpu.h"
#include "qom/object.h"
@@ -55,27 +56,28 @@ struct FslIMX6State {
DeviceState parent_obj;
/*< public >*/
- ARMCPU cpu[FSL_IMX6_NUM_CPUS];
- A9MPPrivState a9mpcore;
- IMX6CCMState ccm;
- IMX6SRCState src;
- IMX7SNVSState snvs;
- IMXSerialState uart[FSL_IMX6_NUM_UARTS];
- IMXGPTState gpt;
- IMXEPITState epit[FSL_IMX6_NUM_EPITS];
- IMXI2CState i2c[FSL_IMX6_NUM_I2CS];
- IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS];
- SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
- IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
- IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
- IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
- ChipideaState usb[FSL_IMX6_NUM_USBS];
- IMXFECState eth;
- MemoryRegion rom;
- MemoryRegion caam;
- MemoryRegion ocram;
- MemoryRegion ocram_alias;
- uint32_t phy_num;
+ ARMCPU cpu[FSL_IMX6_NUM_CPUS];
+ A9MPPrivState a9mpcore;
+ IMX6CCMState ccm;
+ IMX6SRCState src;
+ IMX7SNVSState snvs;
+ IMXSerialState uart[FSL_IMX6_NUM_UARTS];
+ IMXGPTState gpt;
+ IMXEPITState epit[FSL_IMX6_NUM_EPITS];
+ IMXI2CState i2c[FSL_IMX6_NUM_I2CS];
+ IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS];
+ SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
+ IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
+ IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
+ IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
+ ChipideaState usb[FSL_IMX6_NUM_USBS];
+ IMXFECState eth;
+ DesignwarePCIEHost pcie;
+ MemoryRegion rom;
+ MemoryRegion caam;
+ MemoryRegion ocram;
+ MemoryRegion ocram_alias;
+ uint32_t phy_num;
};
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 42f90588251..b7f93d8d9ce 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -22,6 +22,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
+#include "hw/misc/unimp.h"
#include "hw/usb/imx-usb-phy.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
@@ -103,6 +104,8 @@ static void fsl_imx6_init(Object *obj)
object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
+
+ object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
@@ -110,6 +113,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6State *s = FSL_IMX6(dev);
uint16_t i;
+ qemu_irq irq;
unsigned int smp_cpus = ms->smp.cpus;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
@@ -425,6 +429,27 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
FSL_IMX6_WDOGn_IRQ[i]));
}
+ /*
+ * PCIe
+ */
+ sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+
+ /*
+ * PCIe PHY
+ */
+ create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR,
+ FSL_IMX6_PCIe_SIZE);
+
/* ROM memory */
if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
FSL_IMX6_ROM_SIZE, errp)) {
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 2bc3ea3425e..f927878152a 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -547,6 +547,7 @@ config FSL_IMX31
config FSL_IMX6
bool
+ imply PCIE_DEVICES
imply I2C_DEVICES
select A9MPCORE
select IMX
@@ -555,6 +556,7 @@ config FSL_IMX6
select IMX_USBPHY
select WDT_IMX2
select PL310 # cache controller
+ select PCI_EXPRESS_DESIGNWARE
select SDHCI
config ASPEED_SOC
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PULL 00/36] target-arm queue
2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
` (35 preceding siblings ...)
2024-01-26 14:33 ` [PULL 36/36] hw/arm: add PCIe to Freescale i.MX6 Peter Maydell
@ 2024-01-27 13:00 ` Peter Maydell
36 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-01-27 13:00 UTC (permalink / raw)
To: qemu-devel
On Fri, 26 Jan 2024 at 14:33, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 5bab95dc74d43bbb28c6a96d24c810a664432057:
>
> Merge tag 'pull-request-2024-01-24' of https://gitlab.com/thuth/qemu into staging (2024-01-25 12:33:42 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240126
>
> for you to fetch changes up to 5e6be95ed1578c7cfac2082b39384d99fd912508:
>
> hw/arm: add PCIe to Freescale i.MX6 (2024-01-26 12:23:04 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix VNCR fault detection logic
> * Fix A64 scalar SQSHRN and SQRSHRN
> * Fix incorrect aa64_tidcp1 feature check
> * hw/arm/virt.c: Remove newline from error_report() string
> * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
> * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
> * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
> * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
> * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
> * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
> * arm: various include header cleanups
> * cleanups to allow some files to be built only once
> * fsl-imx6ul: Add various missing unimplemented devices
> * docs/system/arm/virt.rst: Add note on CPU features off by default
> * hw/char/imx_serial: Implement receive FIFO and ageing timer
> * target/xtensa: fix OOB TLB entry access
> * bswap.h: Fix const_le64() macro
> * hw/arm: add PCIe to Freescale i.MX6
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PULL 00/36] target-arm queue
@ 2024-02-02 15:36 Peter Maydell
2024-02-03 13:27 ` Peter Maydell
0 siblings, 1 reply; 49+ messages in thread
From: Peter Maydell @ 2024-02-02 15:36 UTC (permalink / raw)
To: qemu-devel
The following changes since commit c3709fde5955d13f6d4f86ab46ef3cc2288ca65e:
Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into staging (2024-02-01 14:42:11 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240202
for you to fetch changes up to f09c2b7ba9908714a3e2f1decd989462536cf731:
hw/arm: Connect SPI Controller to BCM2835 (2024-02-02 13:51:59 +0000)
----------------------------------------------------------------
target/arm: fix exception syndrome for AArch32 bkpt insn
pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset
system/vl.c: Fix handling of '-serial none -serial something'
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
target/arm: Reinstate "vfp" property on AArch32 CPUs
doc/sphinx/hxtool.py: add optional label argument to SRST directive
hw/arm: Check for CPU types in machine_run_board_init() for various boards
pci-host: designware: Limit value range of iATU viewport register
hw/arm: Convert some DPRINTF macros to trace events and guest errors
hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices
hw/arm: Implement BCM2835 SPI Controller
----------------------------------------------------------------
David Woodhouse (1):
doc/sphinx/hxtool.py: add optional label argument to SRST directive
Guenter Roeck (1):
pci-host: designware: Limit value range of iATU viewport register
Hao Wu (2):
hw/net: Add NPCMXXX GMAC device
hw/arm: Add GMAC devices to NPCM7XX SoC
Jan Klötzke (1):
target/arm: fix exception syndrome for AArch32 bkpt insn
Manos Pitsidianakis (6):
hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors
hw/arm/z2: convert DPRINTF to trace events and guest errors
hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports
hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints
hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints
hw/xen: convert stderr prints to error/warn reports
Nabih Estefan Diaz (4):
tests/qtest: Creating qtest for GMAC Module
hw/net: GMAC Rx Implementation
hw/net: GMAC Tx Implementation
tests/qtest: Adding PCS Module test to GMAC Qtest
Peter Maydell (10):
pci: Switch bus reset to 3-phase-reset
vmbus: Switch bus reset to 3-phase-reset
adb: Switch bus reset to 3-phase-reset
hw/s390x/css-bridge: switch virtual-css bus to 3-phase-reset
hw/core: Remove transitional infrastructure from BusClass
system/vl.c: Fix handling of '-serial none -serial something'
qemu-options.hx: Improve -serial option documentation
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
target/arm: Reinstate "vfp" property on AArch32 CPUs
Philippe Mathieu-Daudé (9):
hw/arm/exynos: Add missing QOM parent for CPU cores
hw/arm/exynos: Check for CPU types in machine_run_board_init()
hw/arm/highbank: Add missing QOM parent for CPU cores
hw/arm/highbank: Check for CPU types in machine_run_board_init()
hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/vexpress: Check for CPU types in machine_run_board_init()
hw/arm/zynq: Check for CPU types in machine_run_board_init()
Rayhan Faizel (2):
hw/ssi: Implement BCM2835 SPI Controller
hw/arm: Connect SPI Controller to BCM2835
docs/devel/docs.rst | 12 +-
docs/sphinx/hxtool.py | 16 +
docs/system/arm/raspi.rst | 2 +-
docs/system/i386/xen.rst | 3 +-
include/hw/arm/bcm2835_peripherals.h | 3 +-
include/hw/arm/msf2-soc.h | 3 -
include/hw/arm/npcm7xx.h | 2 +
include/hw/net/npcm_gmac.h | 343 +++++++++++++
include/hw/qdev-core.h | 2 -
include/hw/ssi/bcm2835_spi.h | 81 +++
target/arm/syndrome.h | 8 +
hw/arm/bcm2835_peripherals.c | 17 +-
hw/arm/exynos4210.c | 1 +
hw/arm/exynos4_boards.c | 8 +
hw/arm/highbank.c | 11 +
hw/arm/msf2-soc.c | 3 +-
hw/arm/msf2-som.c | 4 -
hw/arm/musca.c | 1 -
hw/arm/npcm7xx.c | 37 +-
hw/arm/npcm7xx_boards.c | 1 -
hw/arm/strongarm.c | 82 +--
hw/arm/vexpress.c | 12 +-
hw/arm/xen_arm.c | 23 +-
hw/arm/xilinx_zynq.c | 6 +-
hw/arm/z2.c | 27 +-
hw/core/bus.c | 67 ---
hw/hyperv/vmbus.c | 7 +-
hw/input/adb.c | 7 +-
hw/net/npcm_gmac.c | 942 +++++++++++++++++++++++++++++++++++
hw/pci-host/designware.c | 2 +
hw/pci/pci.c | 10 +-
hw/s390x/css-bridge.c | 5 +-
hw/ssi/bcm2835_spi.c | 288 +++++++++++
hw/xen/xen-hvm-common.c | 47 +-
hw/xen/xen-mapcache.c | 59 +--
system/vl.c | 22 +-
target/arm/cpu.c | 4 +
target/arm/helper.c | 19 +
tests/qtest/npcm_gmac-test.c | 344 +++++++++++++
tests/qtest/xlnx-versal-trng-test.c | 19 +-
tests/tcg/aarch64/sysregs.c | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/trace-events | 15 +
hw/net/meson.build | 2 +-
hw/net/trace-events | 19 +
hw/ssi/Kconfig | 4 +
hw/ssi/meson.build | 1 +
hw/xen/trace-events | 21 +-
qemu-options.hx | 16 +-
tests/qtest/meson.build | 1 +
50 files changed, 2388 insertions(+), 244 deletions(-)
create mode 100644 include/hw/net/npcm_gmac.h
create mode 100644 include/hw/ssi/bcm2835_spi.h
create mode 100644 hw/net/npcm_gmac.c
create mode 100644 hw/ssi/bcm2835_spi.c
create mode 100644 tests/qtest/npcm_gmac-test.c
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PULL 00/36] target-arm queue
2024-02-02 15:36 Peter Maydell
@ 2024-02-03 13:27 ` Peter Maydell
0 siblings, 0 replies; 49+ messages in thread
From: Peter Maydell @ 2024-02-03 13:27 UTC (permalink / raw)
To: qemu-devel
On Fri, 2 Feb 2024 at 15:36, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit c3709fde5955d13f6d4f86ab46ef3cc2288ca65e:
>
> Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into staging (2024-02-01 14:42:11 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240202
>
> for you to fetch changes up to f09c2b7ba9908714a3e2f1decd989462536cf731:
>
> hw/arm: Connect SPI Controller to BCM2835 (2024-02-02 13:51:59 +0000)
>
> ----------------------------------------------------------------
> target/arm: fix exception syndrome for AArch32 bkpt insn
> pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset
> system/vl.c: Fix handling of '-serial none -serial something'
> target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
> tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
> target/arm: Reinstate "vfp" property on AArch32 CPUs
> doc/sphinx/hxtool.py: add optional label argument to SRST directive
> hw/arm: Check for CPU types in machine_run_board_init() for various boards
> pci-host: designware: Limit value range of iATU viewport register
> hw/arm: Convert some DPRINTF macros to trace events and guest errors
> hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices
> hw/arm: Implement BCM2835 SPI Controller
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PULL 00/36] target-arm queue
@ 2025-01-28 20:12 Peter Maydell
2025-01-29 19:17 ` Stefan Hajnoczi
0 siblings, 1 reply; 49+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
Hi; here's another arm pullreq; by volume most of this is
refactoring from me, but there are also some bugfixes and
other bits and pieces here.
thanks
-- PMM
The following changes since commit ed734377ab3f3f3cc15d7aa301a87ab6370f2eed:
Merge tag 'linux-user-fix-gupnp-pull-request' of https://github.com/hdeller/qemu-hppa into staging (2025-01-24 14:43:07 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250128-1
for you to fetch changes up to 664280abddcb3cacc9c6204706bb739fcc1316f7:
hw/usb/canokey: Fix buffer overflow for OUT packet (2025-01-28 18:40:19 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/arm: Remove various uses of first_cpu global
* hw/char/imx_serial: Fix reset value of UFCR register
* hw/char/imx_serial: Update all state before restarting ageing timer
* hw/pci-host/designware: Expose MSI IRQ
* hw/arm/stellaris: refactoring, cleanup
* hw/arm/stellaris: map both I2C controllers
* tests/functional: Add a test for the arm microbit machine
* target/arm: arm_reset_sve_state() should set FPSR, not FPCR
* target/arm: refactorings preparatory to FEAT_AFP implementation
* fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed
* fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed
* hw/usb/canokey: Fix buffer overflow for OUT packet
----------------------------------------------------------------
Bernhard Beschow (3):
hw/char/imx_serial: Fix reset value of UFCR register
hw/char/imx_serial: Update all state before restarting ageing timer
hw/pci-host/designware: Expose MSI IRQ
Hongren Zheng (1):
hw/usb/canokey: Fix buffer overflow for OUT packet
Peter Maydell (22):
target/arm: arm_reset_sve_state() should set FPSR, not FPCR
target/arm: Use FPSR_ constants in vfp_exceptbits_from_host()
target/arm: Use uint32_t in vfp_exceptbits_from_host()
target/arm: Define new fp_status_a32 and fp_status_a64
target/arm: Use vfp.fp_status_a64 in A64-only helper functions
target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf()
target/arm: Use fp_status_a32 in vjvct helper
target/arm: Use fp_status_a32 in vfp_cmp helpers
target/arm: Use FPST_A32 in A32 decoder
target/arm: Use FPST_A64 in A64 decoder
target/arm: Remove now-unused vfp.fp_status and FPST_FPCR
target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64
target/arm: Use fp_status_f16_a32 in AArch32-only helpers
target/arm: Use fp_status_f16_a64 in AArch64-only helpers
target/arm: Use FPST_A32_F16 in A32 decoder
target/arm: Use FPST_A64_F16 in A64 decoder
target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16
fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed
fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed
fpu: Fix a comment in softfloat-types.h
target/arm: Remove redundant advsimd float16 helpers
target/arm: Use FPST_A64_F16 for halfprec-to-other conversions
Philippe Mathieu-Daudé (9):
hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'
hw/arm/stellaris: Add 'armv7m' local variable
hw/arm/v7m: Remove use of &first_cpu in machine_init()
hw/arm/stellaris: Link each board schematic
hw/arm/stellaris: Constify read-only arrays
hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000
hw/arm/stellaris: Replace magic numbers by definitions
hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers
hw/arm/stellaris: Map both I2C controllers
Thomas Huth (1):
tests/functional: Add a test for the arm microbit machine
MAINTAINERS | 1 +
hw/usb/canokey.h | 4 --
include/fpu/softfloat-types.h | 10 +--
include/hw/arm/fsl-imx6.h | 4 +-
include/hw/arm/fsl-imx7.h | 4 +-
include/hw/arm/nrf51_soc.h | 2 +-
include/hw/char/imx_serial.h | 2 +-
include/hw/pci-host/designware.h | 1 +
target/arm/cpu.h | 12 ++--
target/arm/tcg/helper-a64.h | 8 ---
target/arm/tcg/translate.h | 32 ++++++---
fpu/softfloat.c | 6 +-
hw/arm/b-l475e-iot01a.c | 2 +-
hw/arm/fsl-imx6.c | 13 +++-
hw/arm/fsl-imx7.c | 13 +++-
hw/arm/microbit.c | 2 +-
hw/arm/mps2-tz.c | 2 +-
hw/arm/mps2.c | 2 +-
hw/arm/msf2-som.c | 2 +-
hw/arm/musca.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/nrf51_soc.c | 18 ++---
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/stellaris.c | 118 +++++++++++++++++++-----------
hw/arm/stm32vldiscovery.c | 2 +-
hw/char/imx_serial.c | 7 +-
hw/pci-host/designware.c | 7 +-
hw/usb/canokey.c | 6 +-
target/arm/cpu.c | 6 +-
target/arm/helper.c | 2 +-
target/arm/tcg/helper-a64.c | 9 ---
target/arm/tcg/sme_helper.c | 6 +-
target/arm/tcg/sve_helper.c | 6 +-
target/arm/tcg/translate-a64.c | 103 ++++++++++++++-------------
target/arm/tcg/translate-sme.c | 4 +-
target/arm/tcg/translate-sve.c | 130 +++++++++++++++++-----------------
target/arm/tcg/translate-vfp.c | 78 ++++++++++----------
target/arm/tcg/vec_helper.c | 22 +++---
target/arm/vfp_helper.c | 73 +++++++++++--------
target/i386/tcg/fpu_helper.c | 8 +--
target/m68k/fpu_helper.c | 2 +-
target/mips/tcg/msa_helper.c | 4 +-
target/rx/op_helper.c | 4 +-
target/tricore/fpu_helper.c | 6 +-
fpu/softfloat-parts.c.inc | 4 +-
hw/arm/Kconfig | 2 +
tests/functional/meson.build | 1 +
tests/functional/test_arm_microbit.py | 31 ++++++++
49 files changed, 452 insertions(+), 337 deletions(-)
create mode 100755 tests/functional/test_arm_microbit.py
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-01-28 20:12 Peter Maydell
@ 2025-01-29 19:17 ` Stefan Hajnoczi
0 siblings, 0 replies; 49+ messages in thread
From: Stefan Hajnoczi @ 2025-01-29 19:17 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PULL 00/36] target-arm queue
@ 2025-07-11 13:33 Peter Maydell
2025-07-13 7:06 ` Stefan Hajnoczi
0 siblings, 1 reply; 49+ messages in thread
From: Peter Maydell @ 2025-07-11 13:33 UTC (permalink / raw)
To: qemu-devel
Hi; this should be my last major pullreq before softfreeze: it has
the nested-virt support, a new Cortex-M4 based board model, and
the CXL-on-arm patchset.
thanks
-- PMM
The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336:
Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into staging (2025-07-07 09:22:41 -0400)
are available in the Git repository at:
https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250711
for you to fetch changes up to 3a323a813fd42fc7c37ef09bc7a714d8e31691ce:
tests/functional: Add a test for the MAX78000 arm machine (2025-07-11 13:30:32 +0100)
----------------------------------------------------------------
target-arm queue:
* New board type max78000fthr
* Enable use of CXL on Arm 'virt' board
* Some more tidyup of ID register handling
* Refactor AT insns and PMU regs into separate source files
* Don't enforce NSE,NS check for EL3->EL3 returns
* hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ
* Allow nested-virtualization with KVM on the 'virt' board
* system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict
* hw/arm/virt-acpi-build: Don't create ITS id mappings by default
* target/arm: Remove unused helper_sme2_luti4_4b
----------------------------------------------------------------
Bernhard Beschow (1):
hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ
Cornelia Huck (5):
arm/cpu: store id_afr0 into the idregs array
arm/cpu: store id_aa64afr{0,1} into the idregs array
arm/cpu: fix trailing ',' for SET_IDREG
arm/cpu: store clidr into the idregs array
arm/kvm: shorten one overly long line
Eric Auger (1):
hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt
Haibo Xu (3):
hw/arm: Allow setting KVM vGIC maintenance IRQ
target/arm/kvm: Add helper to detect EL2 when using KVM
target/arm: Enable feature ARM_FEATURE_EL2 if EL2 is supported
Jackson Donaldson (13):
MAX78000: Add MAX78000FTHR Machine
MAX78000: ICC Implementation
MAX78000: Add ICC to SOC
MAX78000: UART Implementation
MAX78000: Add UART to SOC
MAX78000: GCR Implementation
MAX78000: Add GCR to SOC
MAX78000: TRNG Implementation
MAX78000: Add TRNG to SOC
MAX78000: AES implementation
MAX78000: Add AES to SOC
docs/system: arm: Add max78000 board description
tests/functional: Add a test for the MAX78000 arm machine
Jonathan Cameron (5):
hw/cxl-host: Add an index field to CXLFixedMemoryWindow
hw/cxl: Make the CXL fixed memory windows devices.
hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl
docs/cxl: Add an arm/virt example.
qtest/cxl: Add aarch64 virt test for CXL
Peter Maydell (2):
target/arm: Don't enforce NSE,NS check for EL3->EL3 returns
hw/arm/virt: Allow virt extensions with KVM
Philippe Mathieu-Daudé (1):
system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict
Richard Henderson (4):
target/arm: Drop stub for define_tlb_insn_regs
target/arm: Split out AT insns to tcg/cpregs-at.c
target/arm: Split out performance monitor regs to cpregs-pmu.c
target/arm: Remove helper_sme2_luti4_4b
Shameer Kolothum (1):
hw/arm/virt-acpi-build: Don't create ITS id mappings by default
docs/system/arm/max78000.rst | 37 +
docs/system/arm/virt.rst | 9 +
docs/system/devices/cxl.rst | 11 +
docs/system/target-arm.rst | 1 +
include/hw/arm/max78000_soc.h | 50 +
include/hw/arm/virt.h | 4 +
include/hw/char/max78000_uart.h | 78 ++
include/hw/cxl/cxl.h | 5 +-
include/hw/cxl/cxl_host.h | 5 +-
include/hw/intc/arm_gicv3_common.h | 1 +
include/hw/misc/max78000_aes.h | 68 ++
include/hw/misc/max78000_gcr.h | 131 +++
include/hw/misc/max78000_icc.h | 33 +
include/hw/misc/max78000_trng.h | 35 +
target/arm/cpregs.h | 3 +
target/arm/cpu.h | 6 +-
target/arm/internals.h | 5 +
target/arm/kvm_arm.h | 7 +
target/arm/tcg/helper.h | 1 -
target/arm/cpu-sysregs.h.inc | 4 +
hw/acpi/cxl.c | 76 +-
hw/arm/fsl-imx8mp.c | 4 +
hw/arm/max78000_soc.c | 232 ++++
hw/arm/max78000fthr.c | 50 +
hw/arm/virt-acpi-build.c | 40 +-
hw/arm/virt.c | 52 +-
hw/char/max78000_uart.c | 285 +++++
hw/cxl/cxl-host-stubs.c | 7 +-
hw/cxl/cxl-host.c | 174 ++-
hw/i386/pc.c | 50 +-
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_kvm.c | 29 +
hw/intc/armv7m_nvic.c | 4 +-
hw/misc/max78000_aes.c | 223 ++++
hw/misc/max78000_gcr.c | 351 ++++++
hw/misc/max78000_icc.c | 120 ++
hw/misc/max78000_trng.c | 139 +++
system/qdev-monitor.c | 9 +-
target/arm/cpregs-pmu.c | 1309 +++++++++++++++++++++
target/arm/cpu64.c | 8 +-
target/arm/helper.c | 1813 +----------------------------
target/arm/kvm-stub.c | 5 +
target/arm/kvm.c | 24 +-
target/arm/tcg-stubs.c | 5 -
target/arm/tcg/cpregs-at.c | 519 +++++++++
target/arm/tcg/cpu-v7m.c | 16 +-
target/arm/tcg/cpu32.c | 34 +-
target/arm/tcg/cpu64.c | 68 +-
target/arm/tcg/helper-a64.c | 20 +-
target/arm/tcg/vec_helper.c | 1 -
tests/qtest/cxl-test.c | 58 +-
hw/arm/Kconfig | 15 +
hw/arm/meson.build | 2 +
hw/char/Kconfig | 3 +
hw/char/meson.build | 1 +
hw/misc/Kconfig | 12 +
hw/misc/meson.build | 4 +
target/arm/meson.build | 2 +
target/arm/tcg/meson.build | 1 +
tests/functional/meson.build | 1 +
tests/functional/test_arm_max78000fthr.py | 48 +
tests/qtest/meson.build | 1 +
62 files changed, 4300 insertions(+), 2010 deletions(-)
create mode 100644 docs/system/arm/max78000.rst
create mode 100644 include/hw/arm/max78000_soc.h
create mode 100644 include/hw/char/max78000_uart.h
create mode 100644 include/hw/misc/max78000_aes.h
create mode 100644 include/hw/misc/max78000_gcr.h
create mode 100644 include/hw/misc/max78000_icc.h
create mode 100644 include/hw/misc/max78000_trng.h
create mode 100644 hw/arm/max78000_soc.c
create mode 100644 hw/arm/max78000fthr.c
create mode 100644 hw/char/max78000_uart.c
create mode 100644 hw/misc/max78000_aes.c
create mode 100644 hw/misc/max78000_gcr.c
create mode 100644 hw/misc/max78000_icc.c
create mode 100644 hw/misc/max78000_trng.c
create mode 100644 target/arm/cpregs-pmu.c
create mode 100644 target/arm/tcg/cpregs-at.c
create mode 100755 tests/functional/test_arm_max78000fthr.py
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-07-11 13:33 Peter Maydell
@ 2025-07-13 7:06 ` Stefan Hajnoczi
0 siblings, 0 replies; 49+ messages in thread
From: Stefan Hajnoczi @ 2025-07-13 7:06 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2025-07-13 7:10 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz follow: Atom feed
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2024-01-26 14:33 [PULL 00/36] target-arm queue Peter Maydell
2024-01-26 14:33 ` [PULL 01/36] target/xtensa: fix OOB TLB entry access Peter Maydell
2024-01-26 14:33 ` [PULL 02/36] target/arm: Fix VNCR fault detection logic Peter Maydell
2024-01-26 14:33 ` [PULL 03/36] hw/arm/virt.c: Remove newline from error_report() string Peter Maydell
2024-01-26 14:33 ` [PULL 04/36] hw/arm/musicpal: Convert to qemu_add_kbd_event_handler() Peter Maydell
2024-01-26 14:33 ` [PULL 05/36] hw/arm/allwinner-a10: Unconditionally map the USB Host controllers Peter Maydell
2024-01-26 14:33 ` [PULL 06/36] hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller Peter Maydell
2024-01-26 14:33 ` [PULL 07/36] hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board Peter Maydell
2024-01-26 14:33 ` [PULL 08/36] hw/arm: Add AHCI/SATA controller " Peter Maydell
2024-01-26 14:33 ` [PULL 09/36] hw/arm: Add watchdog timer to Allwinner H40 " Peter Maydell
2024-01-26 14:33 ` [PULL 10/36] hw/arm/exynos4210: Include missing 'exec/tswap.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 11/36] hw/arm/xilinx_zynq: " Peter Maydell
2024-01-26 14:33 ` [PULL 12/36] hw/arm/smmuv3: Include missing 'hw/registerfields.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 13/36] hw/arm/xlnx-versal: Include missing 'cpu.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 14/36] target/arm/cpu-features: Include missing 'hw/registerfields.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 15/36] target/arm/cpregs: " Peter Maydell
2024-01-26 14:33 ` [PULL 16/36] target/arm/cpregs: Include missing 'kvm-consts.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 17/36] target/arm: Rename arm_cpu_mp_affinity Peter Maydell
2024-01-26 14:33 ` [PULL 18/36] target/arm: Create arm_cpu_mp_affinity Peter Maydell
2024-01-26 14:33 ` [PULL 19/36] target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 20/36] target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Peter Maydell
2024-01-26 14:33 ` [PULL 21/36] hw/cpu/a9mpcore: Build it only once Peter Maydell
2024-01-26 14:33 ` [PULL 22/36] hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h' Peter Maydell
2024-01-26 14:33 ` [PULL 23/36] hw/misc/xlnx-versal-crl: Build it only once Peter Maydell
2024-01-26 14:33 ` [PULL 24/36] target/arm: Expose M-profile register bank index definitions Peter Maydell
2024-01-26 14:33 ` [PULL 25/36] hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header Peter Maydell
2024-01-26 14:33 ` [PULL 26/36] target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 27/36] target/arm: Move e2h_access() helper around Peter Maydell
2024-01-26 14:33 ` [PULL 28/36] target/arm: Move GTimer definitions to new 'gtimer.h' header Peter Maydell
2024-01-26 14:33 ` [PULL 29/36] hw/arm: Build various units only once Peter Maydell
2024-01-26 14:33 ` [PULL 30/36] fsl-imx6ul: Add various missing unimplemented devices Peter Maydell
2024-01-26 14:33 ` [PULL 31/36] docs/system/arm/virt.rst: Add note on CPU features off by default Peter Maydell
2024-01-26 14:33 ` [PULL 32/36] hw/char/imx_serial: Implement receive FIFO and ageing timer Peter Maydell
2024-01-26 14:33 ` [PULL 33/36] target/arm: Fix A64 scalar SQSHRN and SQRSHRN Peter Maydell
2024-01-26 14:33 ` [PULL 34/36] bswap.h: Fix const_le64() macro Peter Maydell
2024-01-26 14:33 ` [PULL 35/36] target/arm: Fix incorrect aa64_tidcp1 feature check Peter Maydell
2024-01-26 14:33 ` [PULL 36/36] hw/arm: add PCIe to Freescale i.MX6 Peter Maydell
2024-01-27 13:00 ` [PULL 00/36] target-arm queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2025-07-11 13:33 Peter Maydell
2025-07-13 7:06 ` Stefan Hajnoczi
2025-01-28 20:12 Peter Maydell
2025-01-29 19:17 ` Stefan Hajnoczi
2024-02-02 15:36 Peter Maydell
2024-02-03 13:27 ` Peter Maydell
2020-12-10 11:47 Peter Maydell
2020-12-10 12:51 ` Peter Maydell
2020-09-14 14:06 Peter Maydell
2020-03-12 16:44 Peter Maydell
2020-03-12 20:32 ` Peter Maydell
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