* [PULL] A single RISC-V fixup
@ 2020-03-05 20:05 Palmer Dabbelt
2020-03-05 20:05 ` [PULL] RISC-V: Add a missing "," in riscv_excp_names Palmer Dabbelt
2020-03-06 9:54 ` [PULL] A single RISC-V fixup Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2020-03-05 20:05 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-riscv, qemu-devel
merged tag 'pull-target-arm-20200305'
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200305' into staging (2020-03-05 16:47:37 +0000)
are available in the Git repository at:
git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf4
for you to fetch changes up to fd990e86a7c99f5c99d430160243a3bcc64b0dea:
RISC-V: Add a missing "," in riscv_excp_names (2020-03-05 12:01:43 -0800)
----------------------------------------------------------------
A single RISC-V fixup
This is just a single patch, which fixes a bug found by Coverity.
----------------------------------------------------------------
Palmer Dabbelt (1):
RISC-V: Add a missing "," in riscv_excp_names
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PULL] RISC-V: Add a missing "," in riscv_excp_names
2020-03-05 20:05 [PULL] A single RISC-V fixup Palmer Dabbelt
@ 2020-03-05 20:05 ` Palmer Dabbelt
2020-03-06 9:54 ` [PULL] A single RISC-V fixup Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2020-03-05 20:05 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, qemu-devel, Palmer Dabbelt,
ilippe=20Mathieu-Daud=C3=A9?=
This would almost certainly cause the exception names to be reported
incorrectly. Coverity found the issue (CID 1420223). As per Peter's
suggestion, I've also added a comma at the end of the list to avoid the issue
reappearing in the future.
Fixes: ab67a1d07a ("target/riscv: Add support for the new execption numbers")
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c47d10b739..c0b7023100 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -66,7 +66,7 @@ const char * const riscv_excp_names[] = {
"exec_page_fault",
"load_page_fault",
"reserved",
- "store_page_fault"
+ "store_page_fault",
"reserved",
"reserved",
"reserved",
@@ -74,7 +74,7 @@ const char * const riscv_excp_names[] = {
"guest_exec_page_fault",
"guest_load_page_fault",
"reserved",
- "guest_store_page_fault"
+ "guest_store_page_fault",
};
const char * const riscv_intr_names[] = {
--
2.25.0.265.gbab2e86ba0-goog
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PULL] A single RISC-V fixup
2020-03-05 20:05 [PULL] A single RISC-V fixup Palmer Dabbelt
2020-03-05 20:05 ` [PULL] RISC-V: Add a missing "," in riscv_excp_names Palmer Dabbelt
@ 2020-03-06 9:54 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2020-03-06 9:54 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: open list:RISC-V, QEMU Developers
On Thu, 5 Mar 2020 at 20:06, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> merged tag 'pull-target-arm-20200305'
>
> Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200305' into staging (2020-03-05 16:47:37 +0000)
>
> are available in the Git repository at:
>
> git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf4
>
> for you to fetch changes up to fd990e86a7c99f5c99d430160243a3bcc64b0dea:
>
> RISC-V: Add a missing "," in riscv_excp_names (2020-03-05 12:01:43 -0800)
>
> ----------------------------------------------------------------
> A single RISC-V fixup
>
> This is just a single patch, which fixes a bug found by Coverity.
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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