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From: Peter Maydell <peter.maydell@linaro.org>
To: Francisco Iglesias <francisco.iglesias@xilinx.com>
Cc: edgar.iglesias@xilinx.com, frasse.iglesias@gmail.com,
	alistair@alistair23.me, qemu-devel@nongnu.org,
	alistair23@gmail.com, philmd@redhat.com
Subject: Re: [PATCH v5 12/12] docs/devel: Add documentation for the DMA control interface
Date: Fri, 7 Jan 2022 16:07:17 +0000	[thread overview]
Message-ID: <CAFEAcA8wykmf4ZkpEbj_DrJkmSTU0JSfsar7ysDHcHEg4AzinA@mail.gmail.com> (raw)
In-Reply-To: <20211214110354.21816-13-francisco.iglesias@xilinx.com>

On Tue, 14 Dec 2021 at 11:04, Francisco Iglesias
<francisco.iglesias@xilinx.com> wrote:
>
> Also, since being the author, list myself as maintainer for the file.
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>


> +DmaCtrlIfClass
> +--------------
> +
> +The ``DmaCtrlIfClass`` contains the interface methods that can be
> +implemented by a DMA engine.
> +
> +.. code-block:: c
> +
> +    typedef struct DmaCtrlIfClass {
> +        InterfaceClass parent;
> +
> +        /*
> +         * read: Start a read transfer on the DMA engine implementing the DMA
> +         * control interface
> +         *
> +         * @dma_ctrl: the DMA engine implementing this interface
> +         * @addr: the address to read
> +         * @len: the number of bytes to read at 'addr'
> +         */

The prototype seems to be missing here.

> +    } DmaCtrlIfClass;
> +
> +
> +dma_ctrl_if_read
> +----------------------------
> +
> +The ``dma_ctrl_if_read`` function is used from a model embedding the DMA engine
> +for starting DMA read transfers.
> +
> +.. code-block:: c
> +
> +    /*
> +     * Start a read transfer on a DMA engine implementing the DMA control
> +     * interface.
> +     *
> +     * @dma_ctrl: the DMA engine implementing this interface
> +     * @addr: the address to read
> +     * @len: the number of bytes to read at 'addr'
> +     */
> +    void dma_ctrl_if_read(DmaCtrlIf *dma, hwaddr addr, uint32_t len);

The method says it "starts" the transfer. How does the thing on the
end of the DMA control interface find out when the transfer completes,
or if there were any errors ?

thanks
-- PMM


  reply	other threads:[~2022-01-07 16:09 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-14 11:03 [PATCH v5 00/12] Xilinx Versal's PMC SLCR and OSPI support Francisco Iglesias
2021-12-14 11:03 ` [PATCH v5 01/12] hw/misc: Add a model of Versal's PMC SLCR Francisco Iglesias
2022-01-07 15:50   ` Peter Maydell
2021-12-14 11:03 ` [PATCH v5 02/12] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models Francisco Iglesias
2022-01-07 15:51   ` Peter Maydell
2021-12-14 11:03 ` [PATCH v5 03/12] hw/arm/xlnx-versal: Connect Versal's PMC SLCR Francisco Iglesias
2022-01-07 15:55   ` Peter Maydell
2021-12-14 11:03 ` [PATCH v5 04/12] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header Francisco Iglesias
2021-12-14 11:03 ` [PATCH v5 05/12] hw/dma: Add the DMA control interface Francisco Iglesias
2021-12-14 11:03 ` [PATCH v5 06/12] hw/dma/xlnx_csu_dma: Implement " Francisco Iglesias
2021-12-14 11:03 ` [PATCH v5 07/12] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller Francisco Iglesias
2022-01-07 16:01   ` Peter Maydell
2021-12-14 11:03 ` [PATCH v5 08/12] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model Francisco Iglesias
2022-01-07 15:57   ` Peter Maydell
2021-12-14 11:03 ` [PATCH v5 09/12] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g Francisco Iglesias
2021-12-14 11:03 ` [PATCH v5 10/12] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI Francisco Iglesias
2021-12-14 11:03 ` [PATCH v5 11/12] MAINTAINERS: Add an entry for Xilinx Versal OSPI Francisco Iglesias
2021-12-14 11:03 ` [PATCH v5 12/12] docs/devel: Add documentation for the DMA control interface Francisco Iglesias
2022-01-07 16:07   ` Peter Maydell [this message]
2022-01-14 15:28     ` Francisco Iglesias

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