From: Peter Maydell <peter.maydell@linaro.org>
To: Andrew Jones <drjones@redhat.com>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] hw/arm/virt: gicv3: use all target-list bits
Date: Fri, 24 Jun 2016 17:41:55 +0100 [thread overview]
Message-ID: <CAFEAcA8xQV3PJ7BgFa=ohYDGqyVEtQ9bssoB+0JkGaGJqtaK=w@mail.gmail.com> (raw)
In-Reply-To: <20160624161513.zgqxspxhdre3d67c@hawk.localdomain>
On 24 June 2016 at 17:15, Andrew Jones <drjones@redhat.com> wrote:
> On Fri, Jun 24, 2016 at 06:03:21PM +0200, Andrew Jones wrote:
>> So we can either
>> a) play it safe and always use clusters of 4 for ARM guests, and
>> KVM will get "fixed" when we start managing the guest's MPIDR
>> from userspace, or
>> b) use 8 here, as TCG always has, and KVM does for AArch32 guests.
>> This might be less safe, but also improves SGI efficiency.
>
> Actually AArch32 guests would even use all 16 tlist bits on gicv3, if
> there was a KVM host available to try it. So the (b) option shouldn't
> be "use 8" it should be "don't treat 32-bit guests differently"
KVM AArch32 is 4 CPUs per cluster:
http://lxr.free-electrons.com/source/arch/arm/kvm/coproc.c#L109
thanks
-- PMM
next prev parent reply other threads:[~2016-06-24 16:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-21 18:58 [Qemu-devel] [PATCH] hw/arm/virt: gicv3: use all target-list bits Andrew Jones
2016-06-23 11:15 ` Peter Maydell
2016-06-23 11:50 ` Andrew Jones
2016-06-24 16:03 ` Andrew Jones
2016-06-24 16:15 ` Andrew Jones
2016-06-24 16:41 ` Peter Maydell [this message]
2016-06-24 17:22 ` Andrew Jones
2016-06-24 17:27 ` Peter Maydell
2016-06-27 6:41 ` Andrew Jones
2016-06-27 7:51 ` Marc Zyngier
2016-06-27 8:32 ` Andrew Jones
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