From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51952) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMERN-0007EX-Bb for qemu-devel@nongnu.org; Mon, 03 Aug 2015 08:02:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZMERI-0002mf-Fq for qemu-devel@nongnu.org; Mon, 03 Aug 2015 08:02:01 -0400 Received: from mail-vk0-f51.google.com ([209.85.213.51]:32993) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMERI-0002mV-D4 for qemu-devel@nongnu.org; Mon, 03 Aug 2015 08:01:56 -0400 Received: by vkgc186 with SMTP id c186so41665362vkg.0 for ; Mon, 03 Aug 2015 05:01:56 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <00bd01d0cdbc$b0f97ab0$12ec7010$@samsung.com> From: Peter Maydell Date: Mon, 3 Aug 2015 13:01:36 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v7 6/6] Add gicversion option to virt machine List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Shlomo Pongratz Cc: Shlomo Pongratz , Pavel Fedin , QEMU Developers , Christoffer Dall , Eric Auger On 3 August 2015 at 12:41, Shlomo Pongratz wrote: > > > On Monday, August 3, 2015, Peter Maydell wrote: >> I'm surprised we tell the CPU about the GIC pointer for the >> system register stuff -- I was expecting that we'd give the >> GIC a CPU pointer. (We could in theory implement some >> equivalent of the architected protocol between the redistributors >> and the CPU interfaces, but I think that would be overkill.) > The problem is that each function added as a system's instruction helper to > target-arm/cpu64.c has the signature of void set(CPUARMState *env, > ARMCPRegInfo *ri, uint64_t value) or uint64_t get(CPUARMState *env, > ARMCPRegInfo *ri) > I just mimicked the way armv7m_nvic_XXXX API works. The v7M NVIC is a terrible example to copy -- it is ancient code mostly written before QEMU acquired various useful abstraction layers, and has received very little maintenance since then. > So in a sense the CPU must be familiar with the GIC (as an opaque object of > course). If the GIC just registers a set of system register information with the CPU then the CPU doesn't need to know that it's the GIC providing those system register functions. (You can use define_arm_cp_regs_with_opaque() to define registers such that your callbacks can fish an opaque data pointer back out of ri->opaque, so you can get back to the GIC data structures.) -- PMM