From: Peter Maydell <peter.maydell@linaro.org>
To: Aaron Lindsay <aaron@os.amperecomputing.com>
Cc: qemu-arm <qemu-arm@nongnu.org>,
Alistair Francis <alistair.francis@xilinx.com>,
Wei Huang <wei@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>,
Michael Spradling <mspradli@codeaurora.org>,
Digant Desai <digantd@codeaurora.org>
Subject: Re: [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
Date: Mon, 3 Dec 2018 22:19:48 +0000 [thread overview]
Message-ID: <CAFEAcA900U3amGOGRKGNu+-j9EDhdrZ1U1U5MtoW5BeTo74iOQ@mail.gmail.com> (raw)
In-Reply-To: <20181203204452.GB5549@quinoa.localdomain>
On Mon, 3 Dec 2018 at 20:45, Aaron Lindsay <aaron@os.amperecomputing.com> wrote:
>
> On Nov 30 16:10, Peter Maydell wrote:
> > PMCEID2 and PMCEID3 are only defined from ARMv8.1; before that they
> > are UNDEFINED. So these registers need to be only defined if a
> > suitable feature bit or ID register field check passes.
>
> It looks like we don't currently support any ARMv8.1+ CPUs and don't
> have an entry in the `arm_features` enum for it. I'll plan to add
> ARM_FEATURE_V81 and make defining these registers depend on it, assuming
> any future CPUs supporting it will use that, unless you feel I should do
> something different.
I think that the idea going forward is to prefer an ID
register check of some kind -- Richard ?
thanks
-- PMM
next prev parent reply other threads:[~2018-12-03 22:20 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-20 21:26 [Qemu-devel] [PATCH v8 00/13] More fully implement ARM PMUv3 Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 01/13] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 02/13] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 03/13] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-11-30 16:07 ` Peter Maydell
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 04/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 05/13] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 06/13] target/arm: Implement PMOVSSET Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Aaron Lindsay
2018-11-30 16:10 ` Peter Maydell
2018-12-03 20:44 ` Aaron Lindsay
2018-12-03 22:19 ` Peter Maydell [this message]
2018-12-03 22:57 ` Richard Henderson
2018-12-05 13:00 ` Aaron Lindsay
2018-12-05 15:00 ` Peter Maydell
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 08/13] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Aaron Lindsay
2018-11-30 16:14 ` Peter Maydell
2018-12-03 20:30 ` Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 09/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 10/13] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 11/13] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 12/13] target/arm: Implement PMSWINC Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 13/13] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-11-30 17:13 ` Richard Henderson
2018-11-30 17:56 ` Aaron Lindsay
2018-11-30 18:19 ` Richard Henderson
2018-11-30 19:57 ` Aaron Lindsay
2018-11-30 20:43 ` Richard Henderson
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