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From: Peter Maydell <peter.maydell@linaro.org>
To: Brijen Raval <bjraval123@gmail.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] ARM64 Interrupt handling on QEMU
Date: Thu, 15 Mar 2018 20:42:18 +0000	[thread overview]
Message-ID: <CAFEAcA90d29ge0x+0NLwziZukieee0J9=-Cb_uvmKkWE8p82dA@mail.gmail.com> (raw)
In-Reply-To: <CAGaT8w6dsthvR4GUsbGZLXe0JDGFtP6RkjMPWj5yjmHF8fQs0g@mail.gmail.com>

On 15 March 2018 at 20:24, Brijen Raval <bjraval123@gmail.com> wrote:
> On Thu, Mar 15, 2018 at 2:59 AM Peter Maydell <peter.maydell@linaro.org>
> wrote:
>> Exception 5 is IRQ. (These numbers are all internal to QEMU, and
>> don't have any architectural or guest-visible relevance. They're
>> the EXCP_* constants defined at the top of target/arm/cpu.h.)
>
>
> Yup I checked out the QEMU source and confirmed above. So is there any way
> to find out what is the IRQ for?

You would need to look at what the state of the interrupt controller
is. You can turn on all the tracepoints in the GIC with -d trace:gic*
(though to understand what it's saying you may need to have
some familiarity with the GIC spec and/or look at the code).

thanks
-- PMM

      reply	other threads:[~2018-03-15 20:42 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-15  3:07 [Qemu-devel] ARM64 Interrupt handling on QEMU Brijen Raval
2018-03-15  9:58 ` Peter Maydell
2018-03-15 20:24   ` Brijen Raval
2018-03-15 20:42     ` Peter Maydell [this message]

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