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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 30 Jun 2015 16:42:48 +0100
Message-ID: <CAFEAcA91a67h7PU5oTK9yanWUvWu7SENApDPuCqTLQXZWaFdBw@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH] target-arm: fix write helper for TLBI
	ALLE1IS
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To: Sergey Fedorov <serge.fdrv@gmail.com>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>

On 30 June 2015 at 16:02, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
> TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
> in the same Inner Sharable domain, not just on the current CPU. So we
> must use tlbiall_is_write() here.
>
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
>  target-arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index aa34159..b87afe7 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2441,7 +2441,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>      { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
>        .access = PL2_W, .type = ARM_CP_NO_RAW,
> -      .writefn = tlbiall_write },
> +      .writefn = tlbiall_is_write },
>      { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
>        .access = PL1_W, .type = ARM_CP_NO_RAW,

Nice catch -- applied to target-arm.next, thanks.

-- PMM