From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:43515)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1VudxG-0002AP-68
	for qemu-devel@nongnu.org; Sun, 22 Dec 2013 03:00:10 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1VudxC-0000i9-1C
	for qemu-devel@nongnu.org; Sun, 22 Dec 2013 03:00:06 -0500
Received: from mail-pb0-f41.google.com ([209.85.160.41]:56094)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1VudxB-0000gB-Rp
	for qemu-devel@nongnu.org; Sun, 22 Dec 2013 03:00:01 -0500
Received: by mail-pb0-f41.google.com with SMTP id jt11so4250653pbb.28
	for <qemu-devel@nongnu.org>; Sun, 22 Dec 2013 00:00:01 -0800 (PST)
MIME-Version: 1.0
In-Reply-To: <CAEgOgz5cfu-zpPiP1xnqPg6wiyCbquBh6_=3xcC7ea5yO3Yg=Q@mail.gmail.com>
References: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com>
	<1386060535-15908-19-git-send-email-s.fedorov@samsung.com>
	<CAEgOgz7SNq24uSMdPQru2JchKwL4SBDDWKZRjUtGQJYzgYhBCw@mail.gmail.com>
	<52B29FE5.40705@samsung.com>
	<CAFEAcA8+-MqeY9RzwjAfkcB8RBcNPLj+iqNmUxCWXSAvYMGj8Q@mail.gmail.com>
	<52B4504C.7000707@samsung.com>
	<CAFEAcA8CJw1Lj4ZaG=H3anHUUZ3nsn7ShG7OR3SDbuNiCt-kMQ@mail.gmail.com>
	<CAEgOgz5cfu-zpPiP1xnqPg6wiyCbquBh6_=3xcC7ea5yO3Yg=Q@mail.gmail.com>
From: Peter Maydell <peter.maydell@linaro.org>
Date: Sun, 22 Dec 2013 07:59:40 +0000
Message-ID: <CAFEAcA93m9FV2X8DS88RfD5zem9Sy7YJ5yvu6Nr4TCTA2ahhhA@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP
	registers
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Johannes Winter <johannes.winter@iaik.tugraz.at>, a.basov@samsung.com, Fedorov Sergey <s.fedorov@samsung.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>

On 22 December 2013 01:08, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Sat, Dec 21, 2013 at 12:33 AM, Peter Maydell
> <peter.maydell@linaro.org> wrote:
>> On 20 December 2013 14:12, Fedorov Sergey <s.fedorov@samsung.com> wrote:
>>> I've briefly looked at the v8 ARM ARM. As I can see there is no banked
>>> system control registers in AArch64. Seems the concept is changed to provide
>>> separate registers for each meaningful execution level. Please, correct me
>>> if I am wrong.
>
> Isn't that just another definition of banking?

No: the crn/crm/op values differ for eg ESR_EL1, ESR_EL2 and
ESR_EL3, and if you're in EL3 you can access all three of them
(the access permissions are what stop EL1 from messing with
EL3's ESR). Banked registers are where the same access
instruction reads or writes different state depending on the value
of something else (whether we're secure/nonsecure, in this case).

thanks
-- PMM