From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: Re: [PULL 00/40] riscv-to-apply queue
Date: Tue, 15 Feb 2022 11:39:22 +0000 [thread overview]
Message-ID: <CAFEAcA96Jir1xbWSjhtXJhJkKQ3oR2ck=OFM06OWsyZJep0ecg@mail.gmail.com> (raw)
In-Reply-To: <20220212000031.3946524-1-alistair.francis@opensource.wdc.com>
On Sat, 12 Feb 2022 at 00:07, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
>
> Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08 11:40:08 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212
>
> for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8:
>
> docs/system: riscv: Update description of CPU (2022-02-11 18:31:29 +1000)
>
> ----------------------------------------------------------------
> Fourth RISC-V PR for QEMU 7.0
>
> * Remove old Ibex PLIC header file
> * Allow writing 8 bytes with generic loader
> * Fixes for RV128
> * Refactor RISC-V CPU configs
> * Initial support for XVentanaCondOps custom extension
> * Fix for vill field in vtype
> * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
> * RISC-V AIA support for virt machine
> * Support for svnapot, svinval and svpbmt extensions
Hi; this has format string issues on 32-bit hosts:
https://gitlab.com/qemu-project/qemu/-/jobs/2092600735
../hw/riscv/virt.c: In function 'create_fdt_imsic':
../hw/riscv/virt.c:519:49: error: format '%lx' expects argument of
type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
long unsigned int'} [-Werror=format=]
../hw/riscv/virt.c:569:49: error: format '%lx' expects argument of
type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
long unsigned int'} [-Werror=format=]
Printing hwaddrs needs the HWADDR_PRIx macro. (%l and %ll are
usually the wrong thing in QEMU code as we don't often deal
with real 'long' or 'long long' types.)
-- PMM
next prev parent reply other threads:[~2022-02-15 11:41 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-11 23:59 [PULL 00/40] riscv-to-apply queue Alistair Francis
2022-02-11 23:59 ` [PULL 01/40] include: hw: remove ibex_plic.h Alistair Francis
2022-02-11 23:59 ` [PULL 02/40] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-11 23:59 ` [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-11 23:59 ` [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-11 23:59 ` [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-11 23:59 ` [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 07/40] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 08/40] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-12 0:00 ` [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-12 0:00 ` [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-12 0:00 ` [PULL 11/40] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-12 0:00 ` [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-12 0:00 ` [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 15/40] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-12 0:00 ` [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-12 0:00 ` [PULL 17/40] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-12 0:00 ` [PULL 18/40] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-12 0:00 ` [PULL 20/40] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-12 0:00 ` [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-12 0:00 ` [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-12 0:00 ` [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-12 0:00 ` [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-02-12 0:00 ` [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-02-12 0:00 ` [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-02-12 0:00 ` [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-02-12 0:00 ` [PULL 33/40] docs/system: riscv: Document AIA options for " Alistair Francis
2022-02-12 0:00 ` [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs Alistair Francis
2022-02-12 0:00 ` [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-12 0:00 ` [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-12 0:00 ` [PULL 37/40] target/riscv: add support for svnapot extension Alistair Francis
2022-02-12 0:00 ` [PULL 38/40] target/riscv: add support for svinval extension Alistair Francis
2022-02-12 0:00 ` [PULL 39/40] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-12 0:00 ` [PULL 40/40] docs/system: riscv: Update description of CPU Alistair Francis
2022-02-15 11:39 ` Peter Maydell [this message]
2022-02-16 6:28 ` [PULL 00/40] riscv-to-apply queue Alistair Francis
2022-02-16 6:45 ` Anup Patel
-- strict thread matches above, loose matches on Subject: below --
2025-07-04 11:11 alistair23
2025-07-04 17:50 ` Stefan Hajnoczi
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