* [PULL v2 00/58] tcg patch queue
@ 2024-02-03 7:06 Richard Henderson
2024-02-03 7:06 ` [PULL v2 12/58] target/loongarch: Rename MMU_IDX_* Richard Henderson
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Richard Henderson @ 2024-02-03 7:06 UTC (permalink / raw)
To: qemu-devel
v2: Rebase and resolve target/loongarch conflicts.
Include linux-user/aarch64 vdso fix.
r~
The following changes since commit 29b008927ef6e3fbb70e6607b25d3fcae26a5190:
Merge tag 'pull-nic-config-2-20240202' of git://git.infradead.org/users/dwmw2/qemu into staging (2024-02-02 16:47:36 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240202-2
for you to fetch changes up to 6400be014f80e4c2c246eb8be709ea3a96428233:
linux-user/aarch64: Add padding before __kernel_rt_sigreturn (2024-02-03 16:46:10 +1000)
----------------------------------------------------------------
tests/tcg: Fix multiarch/gdbstub/prot-none.py
hw/core: Convert cpu_mmu_index to a CPUClass hook
tcg/loongarch64: Set vector registers call clobbered
target/sparc: floating-point cleanup
linux-user/aarch64: Add padding before __kernel_rt_sigreturn
----------------------------------------------------------------
Ilya Leoshkevich (1):
tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test
Richard Henderson (57):
include/hw/core: Add mmu_index to CPUClass
target/alpha: Split out alpha_env_mmu_index
target/alpha: Populate CPUClass.mmu_index
target/arm: Split out arm_env_mmu_index
target/arm: Populate CPUClass.mmu_index
target/avr: Populate CPUClass.mmu_index
target/cris: Cache mem_index in DisasContext
target/cris: Populate CPUClass.mmu_index
target/hppa: Populate CPUClass.mmu_index
target/i386: Populate CPUClass.mmu_index
target/loongarch: Populate CPUClass.mmu_index
target/loongarch: Rename MMU_IDX_*
target/m68k: Populate CPUClass.mmu_index
target/microblaze: Populate CPUClass.mmu_index
target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill
target/mips: Split out mips_env_mmu_index
target/mips: Populate CPUClass.mmu_index
target/nios2: Populate CPUClass.mmu_index
target/openrisc: Populate CPUClass.mmu_index
target/ppc: Split out ppc_env_mmu_index
target/ppc: Populate CPUClass.mmu_index
target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index
target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index
target/riscv: Populate CPUClass.mmu_index
target/rx: Populate CPUClass.mmu_index
target/s390x: Split out s390x_env_mmu_index
target/s390x: Populate CPUClass.mmu_index
target/sh4: Populate CPUClass.mmu_index
target/sparc: Populate CPUClass.mmu_index
target/tricore: Populate CPUClass.mmu_index
target/xtensa: Populate CPUClass.mmu_index
include/exec: Implement cpu_mmu_index generically
include/exec: Change cpu_mmu_index argument to CPUState
tcg/loongarch64: Set vector registers call clobbered
target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY
target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL
target/sparc: Remove gen_dest_fpr_F
target/sparc: Introduce gen_{load,store}_fpr_Q
target/sparc: Inline FNEG, FABS
target/sparc: Use i128 for FSQRTq
target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq
target/sparc: Use i128 for FqTOs, FqTOi
target/sparc: Use i128 for FqTOd, FqTOx
target/sparc: Use i128 for FCMPq, FCMPEq
target/sparc: Use i128 for FsTOq, FiTOq
target/sparc: Use i128 for FdTOq, FxTOq
target/sparc: Use i128 for Fdmulq
target/sparc: Remove qt0, qt1 temporaries
target/sparc: Introduce cpu_get_fsr, cpu_put_fsr
target/sparc: Split ver from env->fsr
target/sparc: Clear cexc and ftt in do_check_ieee_exceptions
target/sparc: Merge check_ieee_exceptions with FPop helpers
target/sparc: Split cexc and ftt from env->fsr
target/sparc: Remove cpu_fsr
target/sparc: Split fcc out of env->fsr
target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK
linux-user/aarch64: Add padding before __kernel_rt_sigreturn
include/exec/cpu-all.h | 4 +
include/exec/cpu-common.h | 21 +
include/hw/core/cpu.h | 3 +
target/alpha/cpu.h | 2 +-
target/arm/cpu.h | 13 -
target/arm/internals.h | 5 +
target/avr/cpu.h | 7 -
target/cris/cpu.h | 4 -
target/hexagon/cpu.h | 9 -
target/hppa/cpu.h | 13 -
target/i386/cpu.h | 7 -
target/loongarch/cpu.h | 18 +-
target/m68k/cpu.h | 4 -
target/microblaze/cpu.h | 15 -
target/mips/cpu.h | 6 +-
target/nios2/cpu.h | 6 -
target/openrisc/cpu.h | 12 -
target/ppc/cpu.h | 2 +-
target/riscv/cpu.h | 4 +-
target/rx/cpu.h | 5 -
target/s390x/cpu.h | 2 +-
target/sh4/cpu.h | 10 -
target/sparc/cpu.h | 69 +-
target/sparc/helper.h | 116 ++-
target/tricore/cpu.h | 5 -
target/xtensa/cpu.h | 5 -
accel/tcg/cputlb.c | 22 +-
linux-user/sparc/cpu_loop.c | 2 +-
linux-user/sparc/signal.c | 14 +-
semihosting/uaccess.c | 2 +-
target/alpha/cpu.c | 6 +
target/alpha/translate.c | 2 +-
target/arm/cpu.c | 6 +
target/arm/helper.c | 2 +-
target/arm/tcg/helper-a64.c | 4 +-
target/arm/tcg/mte_helper.c | 18 +-
target/arm/tcg/sve_helper.c | 8 +-
target/arm/tcg/tlb_helper.c | 2 +-
target/avr/cpu.c | 6 +
target/cris/cpu.c | 6 +
target/cris/translate.c | 14 +-
target/hppa/cpu.c | 12 +
target/hppa/mem_helper.c | 2 +-
target/hppa/op_helper.c | 8 +-
target/i386/cpu.c | 10 +
target/i386/tcg/translate.c | 2 +-
target/loongarch/cpu.c | 11 +
target/loongarch/cpu_helper.c | 6 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c | 2 +-
target/m68k/cpu.c | 6 +
target/m68k/op_helper.c | 2 +-
target/microblaze/cpu.c | 18 +-
target/microblaze/helper.c | 3 +-
target/microblaze/mmu.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/cpu.c | 6 +
target/mips/sysemu/physaddr.c | 2 +-
target/mips/tcg/msa_helper.c | 10 +-
target/mips/tcg/sysemu/cp0_helper.c | 2 +-
target/mips/tcg/sysemu/special_helper.c | 2 +-
target/mips/tcg/sysemu/tlb_helper.c | 34 +-
target/nios2/cpu.c | 7 +
target/nios2/translate.c | 2 +-
target/openrisc/cpu.c | 13 +
target/openrisc/translate.c | 2 +-
target/ppc/cpu_init.c | 8 +-
target/ppc/mem_helper.c | 10 +-
target/ppc/mmu_common.c | 4 +-
target/riscv/cpu.c | 6 +
target/riscv/cpu_helper.c | 6 +-
target/riscv/op_helper.c | 4 +-
target/riscv/vector_helper.c | 9 +-
target/rx/cpu.c | 6 +
target/s390x/cpu.c | 6 +
target/s390x/tcg/mem_helper.c | 34 +-
target/sh4/cpu.c | 16 +
target/sparc/cpu.c | 61 +-
target/sparc/fop_helper.c | 510 +++++++------
target/sparc/gdbstub.c | 8 +-
target/sparc/ldst_helper.c | 5 +-
target/sparc/machine.c | 36 +-
target/sparc/mmu_helper.c | 2 +-
target/sparc/translate.c | 799 +++++++--------------
target/tricore/cpu.c | 6 +
target/tricore/helper.c | 2 +-
target/tricore/translate.c | 2 +-
target/xtensa/cpu.c | 6 +
target/xtensa/mmu_helper.c | 2 +-
accel/tcg/ldst_common.c.inc | 42 +-
target/cris/translate_v10.c.inc | 6 +-
.../tcg/insn_trans/trans_privileged.c.inc | 2 +-
tcg/loongarch64/tcg-target.c.inc | 2 +-
linux-user/aarch64/vdso-be.so | Bin 3216 -> 3224 bytes
linux-user/aarch64/vdso-le.so | Bin 3216 -> 3224 bytes
linux-user/aarch64/vdso.S | 4 +
tests/tcg/multiarch/gdbstub/prot-none.py | 2 +-
97 files changed, 1064 insertions(+), 1191 deletions(-)
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PULL v2 12/58] target/loongarch: Rename MMU_IDX_*
2024-02-03 7:06 [PULL v2 00/58] tcg patch queue Richard Henderson
@ 2024-02-03 7:06 ` Richard Henderson
2024-02-03 7:06 ` [PULL v2 35/58] tcg/loongarch64: Set vector registers call clobbered Richard Henderson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2024-02-03 7:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
The expected form is MMU_FOO_IDX, not MMU_IDX_FOO.
Rename to match generic code.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.h | 8 ++++----
target/loongarch/cpu.c | 2 +-
target/loongarch/cpu_helper.c | 4 ++--
target/loongarch/tcg/translate.c | 2 +-
target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +-
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 5dfcfeb3a4..47fd110e81 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -404,15 +404,15 @@ struct LoongArchCPUClass {
*/
#define MMU_PLV_KERNEL 0
#define MMU_PLV_USER 3
-#define MMU_IDX_KERNEL MMU_PLV_KERNEL
-#define MMU_IDX_USER MMU_PLV_USER
-#define MMU_IDX_DA 4
+#define MMU_KERNEL_IDX MMU_PLV_KERNEL
+#define MMU_USER_IDX MMU_PLV_USER
+#define MMU_DA_IDX 4
int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
- return MMU_IDX_USER;
+ return MMU_USER_IDX;
#else
return loongarch_cpu_mmu_index(env_cpu(env), ifetch);
#endif
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index e96159943a..49ced9888e 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
}
- return MMU_IDX_DA;
+ return MMU_DA_IDX;
}
static void loongarch_la464_initfn(Object *obj)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index f68d63f466..b0658773b0 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -171,8 +171,8 @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
{
- int user_mode = mmu_idx == MMU_IDX_USER;
- int kernel_mode = mmu_idx == MMU_IDX_KERNEL;
+ int user_mode = mmu_idx == MMU_USER_IDX;
+ int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
uint32_t plv, base_c, base_v;
int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 235515c629..58674cb268 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -125,7 +125,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
ctx->mem_idx = ctx->plv;
} else {
- ctx->mem_idx = MMU_IDX_DA;
+ ctx->mem_idx = MMU_DA_IDX;
}
/* Bound the number of insns to execute to those left on the page. */
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index 01d457212b..7e4ec93edb 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d)
static void check_mmu_idx(DisasContext *ctx)
{
- if (ctx->mem_idx != MMU_IDX_DA) {
+ if (ctx->mem_idx != MMU_DA_IDX) {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PULL v2 35/58] tcg/loongarch64: Set vector registers call clobbered
2024-02-03 7:06 [PULL v2 00/58] tcg patch queue Richard Henderson
2024-02-03 7:06 ` [PULL v2 12/58] target/loongarch: Rename MMU_IDX_* Richard Henderson
@ 2024-02-03 7:06 ` Richard Henderson
2024-02-03 7:06 ` [PULL v2 58/58] linux-user/aarch64: Add padding before __kernel_rt_sigreturn Richard Henderson
2024-02-03 16:27 ` [PULL v2 00/58] tcg patch queue Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2024-02-03 7:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable, Song Gao
Because there are more call clobbered registers than
call saved registers, we begin with all registers as
call clobbered and then reset those that are saved.
This was missed when we introduced the LSX support.
Cc: qemu-stable@nongnu.org
Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index bab0a173a3..dcf0205458 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -2327,7 +2327,7 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
- tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
+ tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PULL v2 58/58] linux-user/aarch64: Add padding before __kernel_rt_sigreturn
2024-02-03 7:06 [PULL v2 00/58] tcg patch queue Richard Henderson
2024-02-03 7:06 ` [PULL v2 12/58] target/loongarch: Rename MMU_IDX_* Richard Henderson
2024-02-03 7:06 ` [PULL v2 35/58] tcg/loongarch64: Set vector registers call clobbered Richard Henderson
@ 2024-02-03 7:06 ` Richard Henderson
2024-02-03 16:27 ` [PULL v2 00/58] tcg patch queue Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2024-02-03 7:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable, Alex Bennée
Without this padding, an unwind through the signal handler
will pick up the unwind info for the preceding syscall.
This fixes gcc's 30_threads/thread/native_handle/cancel.cc.
Cc: qemu-stable@nongnu.org
Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso")
Resolves: https://linaro.atlassian.net/browse/GNU-974
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240202034427.504686-1-richard.henderson@linaro.org>
---
linux-user/aarch64/vdso-be.so | Bin 3216 -> 3224 bytes
linux-user/aarch64/vdso-le.so | Bin 3216 -> 3224 bytes
linux-user/aarch64/vdso.S | 4 ++++
3 files changed, 4 insertions(+)
diff --git a/linux-user/aarch64/vdso-be.so b/linux-user/aarch64/vdso-be.so
index 6084f3d1a701316004894fcdd739c4e1e0463b68..808206ade824b09d786f6cc34f7cddf80b63130e 100755
GIT binary patch
delta 121
zcmbOrIYV-SKI4pu2Kk&{7{Gw#%fuBAMC1c?^>~k}v|avdxNjSSLfftVb3bgJ!|2S&
z_-6A1CJrVZc?IUH8G;R$7#SF@Om<{a*v!K!&BXX-vIe^~TWO|cva$K*Om;sOMw`hy
ZxXl@VO#Z-a&zLdUfXALuXmSCM0s#EKC)of1
delta 116
zcmbOsIYDxQKI4Rm2Kk&H7{Gw#!^9O2L>8U?-5V_M@!kH(Sx4vJn|*ujLPgija~Pc&
z8DDIEz{J5c`3;N8W)W6tCdL<&4cM*OEF8_<v%@zRviq?xT1-B`ZO-^%@(*r%#)Qch
RJocPi5ThAdCO2?N002V6C;<Qf
diff --git a/linux-user/aarch64/vdso-le.so b/linux-user/aarch64/vdso-le.so
index 947d534ec1899740edbd6921da6bc6e70e2ecd09..941aaf29931193300de1f62097867c282a7e0c74 100755
GIT binary patch
delta 129
zcmbOrIYV-S2IGv0n)#exSQx<I%fyAxMZTVBQ(04AP_*V|Vxp|@=@;x8zb9;-!)U|E
z_-6A>CVnO!c?IUH8G;R$7#SF@Om<{a*v!K!!o>JyvLd?^n`3BUW_royOm=q`Mw`hS
dxy>1WOn%92&zLb;lgFM@hy!9z%j7~Xc>tTxDQW-!
delta 108
zcmbOsIYDxQ2IGW@n)#d`SQx<I!^DNpMK&+G&+g_}w9WI@dn@@euKVesZ-h6`VYFdn
ze6jf^6F<}BH!LcfMOa0c7+*}*WOrgKEO1Fl%G+GX?#{w!F?lDqIpc@PAGz%r6DAw-
M*fVlXF62=M06owo?*IS*
diff --git a/linux-user/aarch64/vdso.S b/linux-user/aarch64/vdso.S
index 34d3a9ebd2..a0ac1487b0 100644
--- a/linux-user/aarch64/vdso.S
+++ b/linux-user/aarch64/vdso.S
@@ -63,7 +63,11 @@ vdso_syscall __kernel_clock_getres, __NR_clock_getres
* For now, elide the unwind info for __kernel_rt_sigreturn and rely on
* the libgcc fallback routine as we have always done. This requires
* that the code sequence used be exact.
+ *
+ * Add a nop as a spacer to ensure that unwind does not pick up the
+ * unwind info from the preceding syscall.
*/
+ nop
__kernel_rt_sigreturn:
/* No BTI C insn here -- we arrive via RET. */
mov x8, #__NR_rt_sigreturn
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PULL v2 00/58] tcg patch queue
2024-02-03 7:06 [PULL v2 00/58] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2024-02-03 7:06 ` [PULL v2 58/58] linux-user/aarch64: Add padding before __kernel_rt_sigreturn Richard Henderson
@ 2024-02-03 16:27 ` Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2024-02-03 16:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, 3 Feb 2024 at 07:07, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> v2: Rebase and resolve target/loongarch conflicts.
> Include linux-user/aarch64 vdso fix.
>
> r~
>
> The following changes since commit 29b008927ef6e3fbb70e6607b25d3fcae26a5190:
>
> Merge tag 'pull-nic-config-2-20240202' of git://git.infradead.org/users/dwmw2/qemu into staging (2024-02-02 16:47:36 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240202-2
>
> for you to fetch changes up to 6400be014f80e4c2c246eb8be709ea3a96428233:
>
> linux-user/aarch64: Add padding before __kernel_rt_sigreturn (2024-02-03 16:46:10 +1000)
>
> ----------------------------------------------------------------
> tests/tcg: Fix multiarch/gdbstub/prot-none.py
> hw/core: Convert cpu_mmu_index to a CPUClass hook
> tcg/loongarch64: Set vector registers call clobbered
> target/sparc: floating-point cleanup
> linux-user/aarch64: Add padding before __kernel_rt_sigreturn
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
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2024-02-03 7:06 [PULL v2 00/58] tcg patch queue Richard Henderson
2024-02-03 7:06 ` [PULL v2 12/58] target/loongarch: Rename MMU_IDX_* Richard Henderson
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