From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, "Clément Chigot" <chigot@adacore.com>,
qemu-stable@nongnu.org
Subject: Re: [PATCH] target/arm: Restrict translation disabled alignment check to VMSA
Date: Thu, 25 Apr 2024 20:18:47 +0100 [thread overview]
Message-ID: <CAFEAcA98UrBLsAXKzLSkUnC2G_RZd56veqUkSGSttoADfkEKGA@mail.gmail.com> (raw)
In-Reply-To: <20240422170722.117409-1-richard.henderson@linaro.org>
On Mon, 22 Apr 2024 at 18:07, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> For cpus using PMSA, when the MPU is disabled, the default memory
> type is Normal, Non-cachable.
>
> Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
> Reported-by: Clément Chigot <chigot@adacore.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>
> Since v9 will likely be tagged tomorrow without this fixed,
> Cc: qemu-stable@nongnu.org
Applied to target-arm.next (with the cc:stable added in and a couple of
trivial tweaks to the comment/commit message), thanks.
-- PMM
next prev parent reply other threads:[~2024-04-25 19:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 17:07 [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Richard Henderson
2024-04-22 17:09 ` Richard Henderson
2024-04-22 21:02 ` Philippe Mathieu-Daudé
2024-04-23 7:16 ` Clément Chigot
2024-04-25 19:18 ` Peter Maydell [this message]
-- strict thread matches above, loose matches on Subject: below --
2024-04-24 17:09 [PATCH 0/5] tcg: Misc improvements Richard Henderson
2024-04-24 17:09 ` [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Richard Henderson
2024-05-03 14:58 ` Philippe Mathieu-Daudé
2024-05-03 14:59 ` Richard Henderson
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