From: Peter Maydell <peter.maydell@linaro.org>
To: Stefan Hajnoczi <stefanha@redhat.com>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
"Steffen Görtz" <mail@steffen-goertz.de>,
"Jim Mussared" <jim@groklearning.com>,
qemu-arm <qemu-arm@nongnu.org>, "Julia Suvorova" <jusual@mail.ru>,
"Joel Stanley" <joel@jms.id.au>
Subject: Re: [Qemu-devel] [RFC 1/2] target/arm: add "cortex-m0" CPU model
Date: Sat, 2 Jun 2018 17:11:03 +0100 [thread overview]
Message-ID: <CAFEAcA9BdH+Qj9S17kVagbTP4B6j+SS64mmSbKu4Yf4H6EKOjQ@mail.gmail.com> (raw)
In-Reply-To: <20180602141446.29982-2-stefanha@redhat.com>
On 2 June 2018 at 15:14, Stefan Hajnoczi <stefanha@redhat.com> wrote:
> Define a "cortex-m0" ARMv6-M CPU model.
>
> Most of the register reset values set by other CPU models are not
> relevant for the cut-down ARMv6-M architecture.
>
> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
> ---
> target/arm/cpu.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 5d60893a07..aac224d809 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1215,6 +1215,16 @@ static void arm11mpcore_initfn(Object *obj)
> cpu->reset_auxcr = 1;
> }
>
> +static void cortex_m0_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + set_feature(&cpu->env, ARM_FEATURE_V6);
> + set_feature(&cpu->env, ARM_FEATURE_M);
> +
> + /* TODO ARMv6-M doesn't support coprocessors, so how is this value accessed? */
> + cpu->midr = 0x410cc200;
The MIDR is a memory-mapped register on M-profile (at 0xed00ed00);
we implement this in hw/intc/armv7m_nvic.c.
> +}
> +
> static void cortex_m3_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> @@ -1796,6 +1806,8 @@ static const ARMCPUInfo arm_cpus[] = {
> { .name = "arm1136", .initfn = arm1136_initfn },
> { .name = "arm1176", .initfn = arm1176_initfn },
> { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
> + { .name = "cortex-m0", .initfn = cortex_m0_initfn,
> + .class_init = arm_v7m_class_init /* TODO rename? */ },
We use v7m for a lot of stuff that's really M-profile in
general (eg the v8m cortex-m33), so I wouldn't worry too
much about renaming the function.
thanks
-- PMM
next prev parent reply other threads:[~2018-06-02 16:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-02 14:14 [Qemu-devel] [RFC 0/2] arm: add skeleton Cortex M0 CPU model Stefan Hajnoczi
2018-06-02 14:14 ` [Qemu-devel] [RFC 1/2] target/arm: add "cortex-m0" " Stefan Hajnoczi
2018-06-02 16:11 ` Peter Maydell [this message]
2018-06-02 14:14 ` [Qemu-devel] [RFC 2/2] arm: add ARMv6-M device container Stefan Hajnoczi
2018-06-02 16:16 ` Peter Maydell
2018-06-04 12:45 ` Stefan Hajnoczi
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