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From: Peter Maydell <peter.maydell@linaro.org>
To: "ishii.shuuichir@fujitsu.com" <ishii.shuuichir@fujitsu.com>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
	"Itaru Kitayama" <itaru.kitayama@gmail.com>,
	"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/arm: Make number of counters in PMCR follow the CPU
Date: Wed, 18 May 2022 11:30:38 +0100	[thread overview]
Message-ID: <CAFEAcA9FvZZjHcSWVVwDE_XxGvFs-rJZgpdkcB7UuSPZj__jUQ@mail.gmail.com> (raw)
In-Reply-To: <TYCPR01MB61604A48D4D67447A373F70CE9CE9@TYCPR01MB6160.jpnprd01.prod.outlook.com>

On Wed, 18 May 2022 at 00:24, ishii.shuuichir@fujitsu.com
<ishii.shuuichir@fujitsu.com> wrote:
>
> Hi, Peter.
>
> > Shuuichirou, Itaru: this is another patch where we need to know
> > an A64FX register value...
>
> Sorry for the late reply.
>
> The initial value of the pmcr_el0 register in A64FX is 0x46014040.
>
> After applying this Peter's patch, should we submit a new patch as a64fx patch from us?
> or do you want to fix your own modifications to the patch that peter has posted?
> Which is the best procedure?

Thanks for looking up the a64fx register value. You don't need to
do anything more -- I'll fix up the TODO comment and put the right
value into this patch, either when I post a v2 of it or else when
I apply it to target-arm.next.

-- PMM


  reply	other threads:[~2022-05-18 10:33 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-13 12:28 [PATCH] target/arm: Make number of counters in PMCR follow the CPU Peter Maydell
2022-05-13 15:47 ` Richard Henderson
2022-05-17 23:24 ` ishii.shuuichir
2022-05-18 10:30   ` Peter Maydell [this message]
2022-05-18 23:33     ` ishii.shuuichir
  -- strict thread matches above, loose matches on Subject: below --
2021-03-11 16:59 Peter Maydell
2021-03-19 10:39 ` Peter Maydell
2021-03-19 10:54 ` Marcin Juszkiewicz
2021-03-26 14:19 ` Richard Henderson
2021-03-31  8:59 ` Zenghui Yu
2021-03-31  9:43   ` Peter Maydell

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